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this document contains information on a product under development at spansion llc. the information is intended to help you eval uate this product. spansion llc reserves the right to change or discontinue work on this proposed product without notice. publication number s71gl512_256_128nb0_00 revision a amendment 1 issue date december 7, 2004 advance information s71gl512nb0/s71gl256nb0/ S71GL128NB0 stacked multi-chip product (mcp) 512/256/128 megabit (32/16/8 m x 16-bit) cmos 3.0 volt-only mirrorbit tm page-mode flash memory with 32 megabit (2m x 16-bit) psram distinctive characteristics mcp features ? power supply voltage of 2.7 to 3.1v high performance ? 90 ns access time (s71gl128n, s71gl256n) ? 100 ns access time (s71gl512n) ? 25 ns page read times ? packages: ? 9.0 x 12.0 mm x 1.2 mm fbga (tld084) (s71gl512n) ? 8.0 x 11.6 mm x 1.2 mm fbga (tla084) (s71gl128n, s71gl256n) ? operating temperature ? -25c to +85c (wireless) ? -40c to +85c (industrial) general description the s71gl series is a product line of stacked multi-chip product (mcp) packages and consists of ? one flash memory die ? one psram the products covered by this document are listed in the table below. for details about their specifications, please refer to the individual constituent datasheets for further details. flash memory density 512 mb 256 mb 128 mb psram density 128 mb 64 mb 32 mb s71gl512nb0 s71gl256nb0 S71GL128NB0 16 mb
2 s71gl512_256_128nb0_00_a1 december 7, 2004 advance information s71gl512nb0/s71gl256nb0/S71GL128NB0 general description . . . . . . . . . . . . . . . . . . . . . . . . 1 product selector guide . . . . . . . . . . . . . . . . . . . . . 4 mcp block diagram (128mb flash + 32mb psram) ..................................5 mcp block diagram (256mb flash + 32mb psram) .................................5 mcp block diagram (512mb flash + 32mb psram) ..................................6 connection diagrams . . . . . . . . . . . . . . . . . . . . . . 7 512 mb flash + 32 mb psram pinout .............................................................7 256 mb flash + 32 mb psram pinout ............................................................8 128 mb flash + 32 mb psram pinout .............................................................9 128 mb flash + 32 mb psram pinout (S71GL128NB0 only) .................. 10 input/output descriptions . . . . . . . . . . . . . . . . . . . 11 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ordering information . . . . . . . . . . . . . . . . . . . . . . . 12 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . 16 s29glxxxn mirrorbit tm flash family datasheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 general description . . . . . . . . . . . . . . . . . . . . . . . 20 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 device bus operations . . . . . . . . . . . . . . . . . . . . . . 23 table 1. device bus operations ........................................... 23 word/byte configuration ................................................................................23 requirements for reading array data .........................................................23 page mode read ............................................................................................. 24 writing commands/command sequences ................................................ 24 write buffer .................................................................................................... 24 accelerated program operation ...............................................................25 autoselect functions .....................................................................................25 standby mode .......................................................................................................25 automatic sleep mode ......................................................................................25 reset#: hardware reset pin .........................................................................25 output disable mode ....................................................................................... 26 table 2. sector address table?s29gl256n ........................... 26 table 3. sector address table?s29gl128n ........................... 33 sector protection ................................................................................................37 persistent sector protection .......................................................................37 password sector protection ........................................................................37 wp# hardware protection .........................................................................37 selecting a sector protection mode .........................................................37 advanced sector protection ...........................................................................38 lock register ........................................................................................................38 table 4. lock register ........................................................ 39 persistent sector protection ...........................................................................39 dynamic protection bit (dyb) ...................................................................39 persistent protection bit (ppb) ................................................................. 40 persistent protection bit lock (ppb lock bit) ...................................... 41 table 5. sector protection schemes ..................................... 41 persistent protection mode lock bit ........................................................... 41 password sector protection ........................................................................... 42 password and password protection mode lock bit ............................... 42 64-bit password ...................................................................................................43 persistent protection bit lock (ppb lock bit) ...........................................43 secured silicon sector flash memory region ............................................43 write protect (wp#) ........................................................................................45 hardware data protection ..............................................................................45 low vcc write inhibit ................................................................................45 write pulse ?glitch? protection ................................................................45 logical inhibit ................................................................................................... 45 power-up write inhibit ............................................................................... 45 common flash memory interface (cfi) . . . . . . . 45 table 6. cfi query identification string ................................ 47 table 7. system interface string.......................................... 47 table 8. device geometry definition..................................... 48 table 9. primary vendor-specific extended query .................. 49 command definitions . . . . . . . . . . . . . . . . . . . . . . 49 reading array data ........................................................................................... 50 reset command ................................................................................................. 50 autoselect command sequence ................................................................... 50 enter secured silicon sector/exit secured silicon sector command sequence ............................................................................. 51 word program command sequence ........................................................... 51 unlock bypass command sequence ........................................................ 52 write buffer programming ......................................................................... 52 accelerated program .....................................................................................53 figure 1. write buffer programming operation....................... 54 figure 2. program operation ............................................... 55 program suspend/program resume command sequence .................... 55 figure 3. program suspend/program resume ........................ 56 chip erase command sequence ................................................................... 56 sector erase command sequence ................................................................ 57 figure 4. erase operation ................................................... 58 erase suspend/erase resume commands .................................................. 58 lock register command set definitions .................................................... 59 password protection command set definitions ...................................... 59 non-volatile sector protection command set definitions ................... 61 global volatile sector protection freeze command set ....................... 61 volatile sector protection command set .................................................. 62 secured silicon sector entry command ..................................................... 62 secured silicon sector exit command ........................................................ 63 command definitions ........................................................................................64 table 10. s29gl512n, s29gl256n, s29gl128n command definitions, x16 ................................................................. 64 table 11. s29gl512n, s29gl256n, s29gl128n command definitions, x8 ................................................................... 67 write operation status ................................................................................... 69 dq7: data# polling ........................................................................................... 70 figure 5. data# polling algorithm ........................................ 71 ry/by#: ready/busy# ........................................................................................ 71 dq6: toggle bit i ............................................................................................... 72 figure 6. toggle bit algorithm ............................................. 73 dq2: toggle bit ii ...............................................................................................73 reading toggle bits dq6/dq2 ..................................................................... 74 dq5: exceeded timing limits ........................................................................ 74 dq3: sector erase timer ................................................................................ 75 dq1: write-to-buffer abort ........................................................................... 75 table 12. write operation status ......................................... 76 absolute maximum ratings . . . . . . . . . . . . . . . . . 76 figure 7. maximum negative overshoot waveform................. 77 figure 8. maximum positive overshoot waveform.......................................................... 77 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . 77 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 78 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 9. test setup........................................................... 79 table 13. test specifications ............................................... 79 key to switching waveforms . . . . . . . . . . . . . . . . 79 figure 10. input waveforms and measurement levels ............ 79 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 80
december 7, 2004 s71gl512_256_128nb0_00_a1 3 advance information read-only operations?s29gl512n only .................................................. 80 read-only operations?s29gl256n only .................................................. 81 read-only operations?s29gl128n only .................................................. 82 figure 11. read operation timings ....................................... 83 figure 12. page read timings .............................................. 83 hardware reset (reset#) .............................................................................. 84 figure 13. reset timings..................................................... 84 erase and program operations?s29gl512n only .................................. 85 erase and program operations?s29gl256n only ................................. 86 erase and program operations?s29gl128n only .................................. 87 figure 14. program operation timings .................................. 88 figure 15. accelerated program timing diagram .................... 88 figure 16. chip/sector erase operation timings ..................... 89 figure 17. data# polling timings (during embedded algorithms) ............................................ 90 figure 18. toggle bit timings (during embedded algorithms) .. 91 figure 19. dq2 vs. dq6 ...................................................... 91 alternate ce# controlled erase and program operations? s29gl512n only ................................................................................................ 92 alternate ce# controlled erase and program operations? s29gl256n only ................................................................................................93 alternate ce# controlled erase and program operations? s29gl128n only ................................................................................................ 94 figure 20. alternate ce# controlled write (erase/program) operation timings .............................................................. 95 latchup characteristics . . . . . . . . . . . . . . . . . . . . 95 erase and programming performance . . . . . . . 96 tsop pin and bga package capacitance . . . . . 96 psram type 1 functional description . . . . . . . . . . . . . . . . . . . . . 97 absolute maximum ratings . . . . . . . . . . . . . . . . . 97 timing test conditions . . . . . . . . . . . . . . . . . . . 103 output load circuit ........................................................................................104 figure 21. output load circuit ........................................... 104 power up sequence . . . . . . . . . . . . . . . . . . . . . . 104 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . 105 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 116 read cycle ........................................................................................................... 116 figure 22. timing of read cycle (ce# = oe# = v il , we# = zz# = v ih )................................................................................ 116 figure 23. timing waveform of read cycle (we# = zz# = v ih ) ......................................................... 117 figure 24. timing waveform of page mode read cycle (we# = zz# = v ih ) ............................................................................ 118 write cycle ......................................................................................................... 119 figure 25. timing waveform of write cycle (we# control, zz# = v ih )................................................................................ 119 figure 26. timing waveform of write cycle (ce# control, zz# = v ih )................................................................................ 119 figure 27. timing waveform of page mode write cycle (zz# = v ih ) ................................................... 120 partial array self refresh (par) ...................................................................120 temperature compensated refresh (for 64mb) ..................................... 121 deep sleep mode ............................................................................................... 121 reduced memory size (for 32m and 16m) .................................................. 121 other mode register settings (for 64m) .................................................... 121 figure 28. mode register .................................................. 122 figure 29. mode register updatetimings (ub#, lb#, oe# are don?t care) ............................................................................. 122 figure 30. deep sleep mode - entry/exit timings (for 64m) ... 123 figure 31. deep sleep mode - entry/exit timings (for 32m and 16m) ........................................................... 123 psram type 7 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . 127 functional description . . . . . . . . . . . . . . . . . . . . 128 power down ......................................................................................................128 power down program sequence ................................................................129 address key ........................................................................................................129 absolute maximum ratings . . . . . . . . . . . . . . . . 130 package capacitance . . . . . . . . . . . . . . . . . . . . . 130 read operation ................................................................................................. 132 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . .134 write operation ............................................................................................... 134 power down parameters ............................................................................... 135 other timing parameters ............................................................................... 135 ac test conditions ......................................................................................... 136 ac measurement output load circuit ..................................................... 136 figure 32. ac output load circuit ...................................... 136 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 137 read timings ....................................................................................................... 137 figure 33. read timing #1 (baisc timing)........................... 137 figure 34. read timing #2 (oe# address access ................. 137 figure 35. read timing #3 (lb#/ub# byte access).............. 138 figure 36. read timing #4 (page address access after ce1# control access for 32m and 64m only)........................................... 138 figure 37. read timing #5 (random and page address access for 32m and 64m only).......................................................... 139 write timings .................................................................................................... 139 figure 38. write timing #1 (basic timing) .......................... 139 figure 39. write timing #2 (we# control) .......................... 140 figure 40. write timing #3-1 (we#/lb#/ub# byte write control) ................................... 140 figure 41. write timing #3-2 (we#/lb#/ub# byte write control) ................................... 141 figure 42. write timing #3-3 (we#/lb#/ub# byte write control) ................................... 141 figure 43. write timing #3-4 (we#/lb#/ub# byte write control) ................................... 142 read/write timings .........................................................................................142 figure 44. read/write timing #1-1 (ce1# control).............. 142 figure 45. read / write timing #1-2 (ce1#/we#/oe# control) ................................................ 143 figure 46. read / write timing #2 (oe#, we# control)........ 143 figure 47. read / write timing #3 (oe#, we#, lb#, ub# control) ......................................... 144 figure 48. power-up timing #1 ......................................... 144 figure 49. power-up timing #2 ......................................... 145 figure 50. power down entry and exit timing...................... 145 figure 51. standby entry timing after read or write ............ 145 figure 52. power down program timing (for 32m/64m only) . 146 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 147
4 s71gl512_256_128nb0_00_a1 december 7, 2004 advance information product selector guide s71gl512nb0 access times at v cc = 2.7 - 3.1 v flash psram max. access time (ns) 100 105 65 max. ce# access time (ns) 100 105 65 max. page access time (t pacc ) 25 25 max. oe# access time (ns) 25 25 s71gl256nb0 access times at v cc = 2.7 - 3.1 v flash psram max. access time (ns) 90 100 65 max. ce# access time (ns) 90 100 65 max. page access time (t pacc ) 25 25 max. oe# access time (ns) 25 25 S71GL128NB0 access times at v cc = 2.7 - 3.1 v flash psram max. access time (ns) 90 100 65 max. ce# access time (ns) 90 100 65 max. page access time (t pacc ) 25 25 max. oe# access time (ns) 25 25
december 7, 2004 s71gl512_256_128nb0_00_a1 5 advance information mcp block diagram (128mb flash + 32mb psram) mcp block diagram (256mb flash + 32mb psram) v id v cc ry/by# psram flash dq15 to dq0 flash-only address shared address ce#f1 ub#s ce2s ce1#s v cc s v cc v ccq v cc f 21 wp#/acc oe# we# reset# ce# wp#/acc oe# we# reset# ry/by# v ss v ssq dq15 to dq0 16 i/o15 to i/o0 16 we# oe# ub# lb#s lb# 21 ce2s ce1#s 2 v id v cc ry/by# psram flash dq15 to dq0 flash-only address shared address ce#f1 ub#s ce2s ce1#s v cc s v cc v ccq v cc f 21 wp#/acc oe# we# reset# ce# wp#/acc oe# we# reset# ry/by# v ss v ssq dq15 to dq0 16 i/o15 to i/o0 16 we# oe# ub# lb#s lb# 21 ce2s ce1#s 3
6 s71gl512_256_128nb0_00_a1 december 7, 2004 advance information mcp block diagram (512mb flash + 32mb psram) v id v cc ry/by# psram flash dq15 to dq0 flash-only address shared address ce#f1 ub#s ce2s ce1#s v cc s v cc v ccq v cc f 21 wp#/acc oe# we# reset# ce# wp#/acc oe# we# reset# ry/by# v ss v ssq dq15 to dq0 16 i/o15 to i/o0 16 we# oe# ub# lb#s lb# 21 ce2s ce1#s 4
december 7, 2004 s71gl512_256_128nb0_00_a1 7 advance information connection diagrams 512 mb flash + 32 mb psram pinout a7 a3 a2 dq8 dq14 ce1#s lb# wp/acc we# a8 a11 c3 c4 c5 c6 c7 c8 a6 ub# rst#f ce2s a19 a12 a15 d2 d3 d4 d5 d6 d7 d8 d9 a5 a18 ry/by# a20 a9 a13 a21 e2 e3 e4 e5 e6 e7 e8 e9 a1 a4 a17 a10 a14 a22 f2 f3 f4 f7 f8 f9 v ss dq1 a0 dq6 a24 a16 g3 g4 g2 g7 g8 g9 ce#f1 dq0 oe# dq9 dq3 dq4 dq13 dq15 rfu h2 h3 h4 h5 h6 h7 h8 h9 dq10 v cc f v cc s dq12 dq7 v ss j2 j3 j4 j5 j6 j7 j8 j9 dq2 dq11 rfu dq5 k3 k8 k4 k5 k6 k7 rfu a23 f5 rfu rfu g5 f6 g6 rfu rfu rfu rfu rfu rfu b3 b4 b5 b6 b7 b8 rfu rfu v cc f rfu rfu rfu l3 l4 l5 l6 l7 l8 b2 b9 c9 c2 k2 k9 l9 l2 rfu rfu rfu rfu rfu rfu rfu rfu a1 a10 m1 m10 nc nc nc nc ram only shared flash only legend reserved fo r future use 84-ball fine-pitch ball grid array 512 mb flash + 32 mb psram pinout (top view, balls facing down)
8 s71gl512_256_128nb0_00_a1 december 7, 2004 advance information 256 mb flash + 32 mb psram pinout a7 a3 a2 dq8 dq14 ce1#s lb# wp/acc we# a8 a11 c3 c4 c5 c6 c7 c8 a6 ub# rst#f ce2s a19 a12 a15 d2 d3 d4 d5 d6 d7 d8 d9 a5 a18 ry/by# a20 a9 a13 a21 e2 e3 e4 e5 e6 e7 e8 e9 a1 a4 a17 a10 a14 a22 f2 f3 f4 f7 f8 f9 v ss dq1 a0 dq6 rfu a16 g3 g4 g2 g7 g8 g9 ce#f1 dq0 oe# dq9 dq3 dq4 dq13 dq15 rfu h2 h3 h4 h5 h6 h7 h8 h9 dq10 v cc f v cc s dq12 dq7 v ss j2 j3 j4 j5 j6 j7 j8 j9 dq2 dq11 rfu dq5 k3 k8 k4 k5 k6 k7 rfu a23 f5 rfu rfu g5 f6 g6 rfu rfu rfu rfu rfu rfu b3 b4 b5 b6 b7 b8 rfu rfu v cc f rfu rfu rfu l3 l4 l5 l6 l7 l8 b2 b9 c9 c2 k2 k9 l9 l2 rfu rfu rfu rfu rfu rfu rfu rfu a1 a10 m1 m10 nc nc nc nc ram only shared flash only legend reserved fo r future use 84-ball fine-pitch ball grid array 256 mb flash + 32 mb psram pinout (top view, balls facing down)
december 7, 2004 s71gl512_256_128nb0_00_a1 9 advance information 128 mb flash + 32 mb psram pinout a7 a3 a2 dq8 dq14 ce1#s lb# wp/acc we# a8 a11 c3 c4 c5 c6 c7 c8 a6 ub# rst#f ce2s a19 a12 a15 d2 d3 d4 d5 d6 d7 d8 d9 a5 a18 ry/by# a20 a9 a13 a21 e2 e3 e4 e5 e6 e7 e8 e9 a1 a4 a17 a10 a14 a22 f2 f3 f4 f7 f8 f9 v ss dq1 a0 dq6 rfu a16 g3 g4 g2 g7 g8 g9 ce#f1 dq0 oe# dq9 dq3 dq4 dq13 dq15 rfu h2 h3 h4 h5 h6 h7 h8 h9 dq10 v cc f v cc s dq12 dq7 v ss j2 j3 j4 j5 j6 j7 j8 j9 dq2 dq11 rfu dq5 k3 k8 k4 k5 k6 k7 rfu rfu f5 rfu rfu g5 f6 g6 rfu rfu rfu rfu rfu rfu b3 b4 b5 b6 b7 b8 rfu rfu v cc f rfu rfu rfu l3 l4 l5 l6 l7 l8 b2 b9 c9 c2 k2 k9 l9 l2 rfu rfu rfu rfu rfu rfu rfu rfu a1 a10 m1 m10 nc nc nc nc ram only shared flash only legend reserved fo r future use 84-ball fine-pitch ball grid array 128 mb flash + 32 mb psram pinout (top view, balls facing down)
10 s71gl512_256_128nb0_00_a1 december 7, 2004 advance information 128 mb flash + 32 mb psram pinout (S71GL128NB0 only) note: ball l5 (rfu) is a v cc on an 84-ball package; therefore, it is recommended that l5 not be connected to v ss . e4 ub# f4 a18 g4 a17 h4 dq1 j4 dq9 k4 dq10 dq2 d4 e6 ce2s a20 j6 dq4 k6 vccs rfu d6 rfu e7 a19 f7 a9 g7 a10 h7 dq6 j7 dq13 k7 dq12 dq5 d7 e5 rst#f ry/by# j5 dq3 k5 vccf dq11 d5 rfu e8 a12 f8 a13 g8 a14 h8 rfu j8 dq15 k8 dq7 dq14 d8 e9 f9 a21 g9 a22 h9 a16 j9 rfu vss e3 a6 f3 a5 g3 a4 h3 vss j3 oe# k3 dq0 ce1#s dq8 d3 e2 f2 a2 g2 a1 h2 a0 j2 ce#f h6 h5 b6 b5 ram only shared flash only legend reserved fo r future use rfu rfu* l6 l5 lb# c4 we# c6 a8 c7 wp/acc c5 a11 c8 a7 c3 a3 d2 a15 d9 a1 nc a10 nc m1 m10 nc nc 64-ball fine-pitch ball grid array (top view, balls facing down)
december 7, 2004 s71gl512_256_128nb0_00_a1 11 advance information input/output descriptions a24-a0 = 25 address inputs (512 mb) a23-a0 = 24 address inputs (256 mb) a22-a0 = 23 address inputs (128 mb) dq15-dq0 = data input/output oe# = output enable input. asynchronous relative to clk for the burst mode. we# = write enable input. v ss = ground nc = no connect; not connected internally reset# = hardware reset input. low = device resets and returns to reading array data wp#/acc = hardware write protect input / programming acceleration input. ce1#s, ce2s = chip-enable input for psram. ce#f1 = chip-enable input for flash 1. v cc f = flash 3.0 volt-only single power supply. v cc s = psram power supply. ub#s = upper byte control (psram). lb#s = lower byte control (psram). rfu = reserved for future use. ry/by# = ready/busy output. logic symbol max+1 16 dq15?dq0 a max *?a0 we# wp#/acc we# reset# ce1#s ry/by# ub# ce2s oe# *max = a24 lb# ce#f1
12 s71gl512_256_128nb0_00_a1 december 7, 2004 advance information ordering information the order number (valid combination) is formed by the following: s71gl 512 n b0 ba w a b 0 packing type 0=tray 2 = 7? tape and reel 3 = 13? tape and reel model number b = refer to the valid combinations table package modifier a = 1.2 mm height, 8 x 11.6 mm, 84 balls fbga e = 1.2 mm height, 9 x 12.0 mm, 84 balls fbga 9 = 1.2 mm height, 8 x 11.6 mm, 64 balls fbga temperature range w = wireless (-25 c to +85 c) i = industrial (-40 c to +85 c) package type ba = very thin fine-pitch bga lead (pb)-free compliant package bf = very thin fine-pitch bga lead (pb)-free package psram density b0 = 32 mb psram process technology n = 110 nm, mirrorbit tm technology flash density 512 = 512 mb 256 = 256 mb 128 = 128 mb product family s71gl multi-chip product (mcp) 3.0 volt-only uniform sector page mode flash memory
december 7, 2004 s71gl512_256_128nb0_00_a1 13 advance information s71gl512nb0 valid combinations flash initial/page speed (ns) address sector protection (p)sram supplier (p)sram type/ access time (ns) package type package marking base ordering part number package & temperature package modifier/ model number packing type s71gl512nb0 baw ek 0, 2, 3 (note 1) 105/25 lowest add type 1 65/25 9mmx12mm 84-ball lead (pb)-free compliant (note 2) ep highest add eu lowest add type 7 ez highest add ej 100/25 lowest add type 1 en highest add et lowest add type 7 ey highest add s71gl512nb0 bfw ek 0, 2, 3 (note 1) 105/25 lowest add type 1 65/25 9mmx12mm 84-ball lead (pb)-free ep highest add eu lowest add type 7 ez highest add ej 100/25 lowest add type 1 en highest add et lowest add type 7 ey highest add notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations.
14 s71gl512_256_128nb0_00_a1 december 7, 2004 advance information s71gl256nb0 valid combinations flash initial/ page speed (ns) address sector protection (p)sram supplier (p)sram type/ access time (ns) package type package marking base ordering part number package & temperature package modifier/ model number packing type s71gl256nb0 baw ak 0, 2, 3 (note 1) 100/25 lowest add typ e 1 65/25 8mmx11.6mm 84-ball lead (pb)-free compliant (note 2) ap highest add au lowest add typ e 7 az highest add aj 90/25 lowest add typ e 1 an highest add at lowest add typ e 7 ay highest add s71gl256nb0 bfw ak 0, 2, 3 (note 1) 100/25 lowest add typ e 1 65/25 8mmx11.6mm 84-ball lead (pb)-free ap highest add au lowest add typ e 7 az highest add aj 90/25 lowest add typ e 1 an highest add at lowest add typ e 7 ay highest add notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations.
december 7, 2004 s71gl512_256_128nb0_00_a1 15 advance information S71GL128NB0 valid combinations flash initial/ page speed (ns) address sector protection (p)sram supplier (p)sram type/ access time (ns) package type package marking base ordering part number package & temperature package modifier/ model number packing type S71GL128NB0 baw 9k 0, 2, 3 (note 1) 100/25 lowest add ty p e 1 65/25 8mmx11.6mm 64-ball lead (pb)-free compliant (note 2) 9p highest add 9u lowest add ty p e 7 9z highest add 9j 90/25 lowest add ty p e 1 9n highest add 9t lowest add ty p e 7 9y highest add ak 100/25 lowest add ty p e 1 8mmx11.6mm 84-ball lead (pb)-free compliant ap highest add au lowest add ty p e 7 az highest add aj 90/25 lowest add ty p e 1 an highest add at lowest add ty p e 7 ay highest add S71GL128NB0 bfw 9k 0, 2, 3 (note 1) 100/25 lowest add ty p e 1 65/25 8mmx11.6mm 64-ball lead (pb)-free compliant 9p highest add 9u lowest add ty p e 7 9z highest add 9j 90/25 lowest add ty p e 1 9n highest add 9t lowest add ty p e 7 9y highest add ak 100/25 lowest add ty p e 1 8mmx11.6mm 84-ball lead (pb)-free ap highest add au lowest add ty p e 7 az highest add aj 90/25 lowest add ty p e 1 an highest add at lowest add ty p e 7 ay highest add notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations.
16 s71gl512_256_128nb0_00_a1 december 7, 2004 advance information physical dimensions tld084?84-ball fine-pitch ball grid array (fbga) 9.0 x 12.0 x1.2 mm mcp compatible package note: bsc is an ansi standard for basic space centering 3367\ 16-038.22a package tld 084 jedec n/a d x e 12.00 mm x 9.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.97 body thickness d 12.00 bsc. body size e 9.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 84 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b10,c1,c10,d1,d10 e1,e10,f1,f10,g1,g10 h1,h10,j1,j10,k1,k10 l1,l10,m2,m3,m4,m5,m6, m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.08 0.20 c c 6 b side view 84x a1 a2 a 0.15 m c a b 0.08 m c bottom view ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd a e b c 0.15 (2x) d c 0.15 (2x) index mark 10 top view corner pin a1
december 7, 2004 s71gl512_256_128nb0_00_a1 17 advance information tla084?84-ball fine-pitch ball grid array (fbga) 8.0 x 11.6 x1.2 mm mcp compatible package note: bsc is an ansi standard for basic space centering 3372-2 \ 16-038.22a package tla 084 jedec n/a d x e 11.60 mm x 8.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.97 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 84 ball count ? b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b10,c1,c10,d1,d10, e1,e10,f1,f10,g1,g10, h1,h10,j1,j10,k1,k10,l1,l10, m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 84x a1 a2 a 0.15 c a b m c m 0.08 pin a1 ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view
18 s71gl512_256_128nb0_00_a1 december 7, 2004 advance information tla064?64-ball fine-pitch ball grid array (fbga) 8.0 x 11.6 x1.2 mm mcp compatible package note: bsc is an ansi standard for basic space centering. 3352 \ 16-038.22a package tla 064 jedec n/a d x e 11.60 mm x 8.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.97 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 64 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b2,b3,b4,b7,b8,b9,b10 c1,c2,c9,c10,d1,d10,e1,e10, f1,f5,f6,f10,g1,g5,g6,g10 h1,h10,j1,j10,k1,k2,k9,k10 l1,l2,l3,l4,l7,l8,l9,l10 m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.20 c 0.08 c b 64x 6 0.08 m c 0.15 m c a b a2 a a1 side view l m ed corner e1 7 se d1 a b dc e f hg 10 8 9 7 5 6 4 2 3 j k 1 ee sd bottom view pin a1 7 10 index mark c 0.15 (2x) (2x) c 0.15 b a d e pin a1 top view corner
this document contains information on a product under development at spansion llc. the information is intended to help you eval uate this product. spansion llc reserves the right to change or discontinue work on this proposed product without notice. publication number s29glxxxn_00 revision a amendment 4 issue date june 14, 2004 advance information s29glxxxn mirrorbit tm flash family s29gl512n, s29gl256n, s29gl128n 512 megabit, 256 megabit, and 128 megabit, 3.0 volt-only page mode flash memory featuring 110 nm mirrorbit process technology datasheet distinctive characteristics architectural advantages ? single power supply operation ? 3 volt read, erase, and program operations ? enhanced versatilei/o ? ? all input levels (address, control, and dq input levels) and outputs are determined by voltage on v io input. v io range is 1.65 to v cc ? manufactured on 110 nm mirrorbit process technology ? secured silicon sector region ? 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random electronic serial number, accessible through a command sequence ? may be programmed and locked at the factory or by the customer ? flexible sector architecture ? s29gl512n: five hundred twelve 64 kword (128 kbyte) sectors ? s29gl256n: two hundred fifty-six 64 kword (128 kbyte) sectors ? s29gl128n: one hundred twenty-eight 64 kword (128 kbyte) sectors ? compatibility with jedec standards ? provides pinout and software compatibility for single- power supply flash, and superior inadvertent write protection ? 100,000 erase cycles per sector typical ? 20-year data retention typical performance characteristics ? high performance ? 80 ns access time (s29gl128n, s29gl256n), 90 ns access time (s29gl512n) ? 8-word/16-byte page read buffer ? 25 ns page read times ? 16-word/32-byte write buffer reduces overall programming time for multiple-word updates ? low power consumption (typical values at 3.0 v, 5 mhz) ? 25 ma typical active read current; ? 50 ma typical erase/program current ? 1 a typical standby mode current software & hardware features ? software features ? program suspend & resume: read other sectors before programming operation is completed ? erase suspend & resume: read/program other sectors before an erase operation is completed ? data# polling & toggle bits provide status ? unlock bypass program command reduces overall multiple-word or byte programming time ? cfi (common flash interfac e) compliant: allows host system to identify and accommodate multiple flash devices ? hardware features ? advanced sector protection ? wp#/acc input accelerates programming time (when high voltage is applied) for greater throughput during system production. protects first or last sector regardless of sector protection settings ? hardware reset input (reset#) resets device ? ready/busy# output (ry/by#) detects program or erase cycle completion
20 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information general description the gl512/256/128n family of devices are 3.0v single power flash memory man- ufactured using 110 nm mirrorbit technology. the gl512n is a 512 mbit, organized as 33,554,432 words or 67,108,864 bytes. the gl256n is a 256 mbit, organized as 16,777,216 words or 33,554,432 bytes. the gl128n is a 128 mbit, organized as 8,388,608 words or 16,777,216 bytes. the devices have a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the byte# input. the device can be programmed either in the host system or in standard eprom programmers. access times as fast as 90 ns (gl128n, gl256n) or 100 ns (gl512n) are available. each device requires only a single 3.0 volt power supply for both read and write functions. in addition to a v cc input, a high-voltage accelerated program ( wp#/ acc) input provides shorter programming times through increased cur- rent. this feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. the devices are entirely command set compatible with the jedec single- power-supply flash standard . commands are written to the device using standard microprocessor write timing. write cycles also internally latch addresses and data needed for the programming and erase operations. the sector erase architecture allows memory sectors to be erased and repro- grammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. device programming and erasure are initiated through command sequences. once a program or erase operation has begun, the host system need only poll the dq7 (data# polling) or dq6 (toggle) status bits or monitor the ready/busy# (ry/by#) output to determine whether the operation is complete. to facilitate programming, an unlock bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. hardware data protection measures include a low v cc detector that automat- ically inhibits write operations during power transitions. persistent sector protection provides in-system, command-enabled protection of any combina- tion of sectors using a single power supply at v cc . password sector protection prevents unauthorized write and erase operations in any combination of sectors through a user-defined 64-bit password. the erase suspend/erase resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. the program suspend/program resume fea- ture enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. the hardware reset# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the host system to read boot-up firmware from the flash memory device. the device reduces power consumption in the standby mode when it detects specific voltage levels on ce# and reset#, or when addresses have been stable for a specified period of time.
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 21 advance information the secured silicon sector provides a 128-word/256-byte area for code or data that can be permanently protected. once this sector is protected, no further changes within the sector can occur. the write protect (wp#/acc) feature protects the first or last sector by as- serting a logic low on the wp# pin. mirrorbit flash technology combines years of flash memory manufacturing expe- rience to produce the highest levels of quality, reliability and cost effectiveness. the device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. the data is programmed using hot electron injection.
june 14, 2004 s29glxxxn_00a4 s29glxxxn mirrorbit tm flash family 22 advance information block diagram input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss v io we# wp#/acc byte# ce# oe# stb stb dq15 ? dq0 (a-1) sector switches ry/by# reset# data latch y-gating cell matrix address latch a max **?a0
june 14, 2004 s29glxxxn_00a4 s29glxxxn mirrorbit tm flash family 23 advance information device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. ta b l e 1 . device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 11.5?12.5v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. addresses are amax:a0 in word mode; a max :a-1 in byte mode. sector addresses are a max :a16 in both modes. 2. if wp# = v il , the first or last sector group remains protected. if wp# = v ih , the first or last sector will be protected or unprotected as determined by the method described in ?write protect (wp#)?. all sectors are unprotected when shipped from the factory (the secured silicon sector may be factory protected depending on version ordered.) 3. d in or d out as required by command sequence, data polling, or sector protect algorithm (see figure 2). word/byte configuration the byte# pin controls whether the device data i/o pins operate in the byte or word configuration. if the byte# pin is set at logic ?1?, the device is in word con- figuration, dq0?dq15 are active and controlled by ce# and oe#. if the byte# pin is set at logic ?0?, the device is in byte configuration, and only data i/o pins dq0?dq7 are active and controlled by ce# and oe#. the data i/ o pins dq8?dq14 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. we# should remain at v ih . operation ce# oe# we # reset# wp# acc addresses (note 2) dq0? dq7 dq8?dq15 byte# = v ih byte# = v il read l l h h x x a in d out d out dq8?dq14 = high-z, dq15 = a-1 write (program/erase) l h l h (note 2) x a in (note 3) (note 3) accelerated program l h l h (note 2) v hh a in (note 3) (note 3) standby v cc 0.3 v xx v cc 0.3 v x h x high-z high-z high-z output disable l h h h x x x high-z high-z high-z reset x x x l x x x high-z high-z high-z
24 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?reading array data? for more information. refer to the ac read-only op- erations table for timing specifications and to figure 11 for the timing diagram. refer to the dc characteristics table for the active current specification on read- ing array data. page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read operation. this mode provides faster read access speed for random locations within a page. the page size of the device is 8 words/16 bytes. the appropriate page is selected by the higher address bits a(max)?a3. address bits a2?a0 in word mode (a2?a-1 in byte mode) determine the specific word within a page. this is an asynchronous operation; the microprocessor supplies the specific word location. the random or initial page access is equal to t acc or t ce and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t pacc . when ce# is de-asserted and reasserted for a subsequent access, the access time is t acc or t ce . fast page mode accesses are obtained by keeping the ?read-page addresses? constant and changing the ?intra-read page? addresses. writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . the device features an unlock bypass mode to facilitate faster programming. once the device enters the unlock bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. the ?word/byte program command sequence? section has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sectors, or the entire device. table 2 indicates the address space that each sector occupies. refer to the dc characteristics table for the active current specification for the write mode. the ac characteristics section contains timing specification tables and timing diagrams for write operations. write buffer write buffer programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. this results in faster effective programming time than the standard programming algorithms. see ?write buffer? for more information.
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 25 advance information accelerated program operation the device offers accelerated program operations through the acc function. this is one of two functions provided by the wp#/acc pin. this function is primarily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device automatically enters the afore- mentioned unlock bypass mode, temporarily unprotects any protected sector groups, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command se- quence as required by the unlock bypass mode. removing v hh from the wp#/ acc pin returns the device to normal operation. note that the wp#/acc pin must not be at v hh for operations other than accelerated programming, or device dam- age may result. wp# has an internal pullup; when unconnected, wp# is at v ih . autoselect functions if the system writes the autoselect command sequence, the device enters the au- toselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the ?autoselect command sequence? section on page 50 sections for more information. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v io 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v io 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or programming, the device draws ac- tive current until the operation is completed. refer to the ?dc characteristics? section on page 78 for the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the de- vice automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# con- trol signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. refer to the ?dc characteristics? section on page 78 for the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of resetting the device to reading array data. when the reset# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the op-
26 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information eration that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of th e reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc5 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. refer to the ac characteristics tables for reset# parameters and to figure 13 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state. ta b l e 2 . sector address table?s29gl256n sector a23?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) sa0 0 0 0 0 0 0 0 0 128/64 0000000?001ffff 0000000?000ffff sa1 0 0 0 0 0 0 0 1 128/64 0020000?003ffff 0010000?001ffff sa2 0 0 0 0 0 0 1 0 128/64 0040000?005ffff 0020000?002ffff sa3 0 0 0 0 0 0 1 1 128/64 0060000?007ffff 0030000?003ffff sa4 0 0 0 0 0 1 0 0 128/64 0080000?009ffff 0040000?004ffff sa5 0 0 0 0 0 1 0 1 128/64 00a0000?00bffff 0050000?005ffff sa6 0 0 0 0 0 1 1 0 128/64 00c0000?00dffff 0060000?006ffff sa7 0 0 0 0 0 1 1 1 128/64 00e0000?00fffff 0070000?007ffff sa8 0 0 0 0 1 0 0 0 128/64 0100000?011ffff 0080000?008ffff sa9 0 0 0 0 1 0 0 1 128/64 0120000?013ffff 0090000?009ffff sa10 0 0 0 0 1 0 1 0 128/64 0140000?015ffff 00a0000?00affff sa11 0 0 0 0 1 0 1 1 128/64 0160000?017ffff 00b0000?00bffff sa12 0 0 0 0 1 1 0 0 128/64 0180000?019ffff 00c0000?00cffff sa13 0 0 0 0 1 1 0 1 128/64 01a0000?01bffff 00d0000?00dffff sa14 0 0 0 0 1 1 1 0 128/64 01c0000?01dffff 00e0000?00effff sa15 0 0 0 0 1 1 1 1 128/64 01e0000?01fffff 00f0000?00fffff sa16 0 0 0 1 0 0 0 0 128/64 0200000?021ffff 0100000?010ffff sa17 0 0 0 1 0 0 0 1 128/64 0220000?023ffff 0110000?011ffff sa18 0 0 0 1 0 0 1 0 128/64 0240000?025ffff 0120000?012ffff sa19 0 0 0 1 0 0 1 1 128/64 0260000?027ffff 0130000?013ffff sa20 0 0 0 1 0 1 0 0 128/64 0280000?029ffff 0140000?014ffff sa21 0 0 0 1 0 1 0 1 128/64 02a0000?02bffff 0150000?015ffff sa22 0 0 0 1 0 1 1 0 128/64 02c0000?02dffff 0160000?016ffff
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 27 advance information sa23 0 0 0 1 0 1 1 1 128/64 02e0000?02fffff 0170000?017ffff sa24 0 0 0 1 1 0 0 0 128/64 0300000?031ffff 0180000?018ffff sa25 0 0 0 1 1 0 0 1 128/64 0320000?033ffff 0190000?019ffff sa26 0 0 0 1 1 0 1 0 128/64 0340000?035ffff 01a0000?01affff sa27 0 0 0 1 1 0 1 1 128/64 0360000?037ffff 01b0000?01bffff sa28 0 0 0 1 1 1 0 0 128/64 0380000?039ffff 01c0000?01cffff sa29 0 0 0 1 1 1 0 1 128/64 03a0000?03bffff 01d0000?01dffff sa30 0 0 0 1 1 1 1 0 128/64 03c0000?03dffff 01e0000?01effff sa31 0 0 0 1 1 1 1 1 128/64 03e0000?03fffff 01f0000?01fffff sa32 0 0 1 0 0 0 0 0 128/64 0400000?041ffff 0200000?020ffff sa33 0 0 1 0 0 0 0 1 128/64 0420000?043ffff 0210000?021ffff sa34 0 0 1 0 0 0 1 0 128/64 0440000?045ffff 0220000?022ffff sa35 0 0 1 0 0 0 1 1 128/64 0460000?047ffff 0230000?023ffff sa36 0 0 1 0 0 1 0 0 128/64 0480000?049ffff 0240000?024ffff sa37 0 0 1 0 0 1 0 1 128/64 04a0000?04bffff 0250000?025ffff sa38 0 0 1 0 0 1 1 0 128/64 04c0000?04dffff 0260000?026ffff sa39 0 0 1 0 0 1 1 1 128/64 04e0000?04fffff 0270000?027ffff sa40 0 0 1 0 1 0 0 0 128/64 0500000?051ffff 0280000?028ffff sa41 0 0 1 0 1 0 0 1 128/64 0520000?053ffff 0290000?029ffff sa42 0 0 1 0 1 0 1 0 128/64 0540000?055ffff 02a0000?02affff sa43 0 0 1 0 1 0 1 1 128/64 0560000?057ffff 02b0000?02bffff sa44 0 0 1 0 1 1 0 0 128/64 0580000?059ffff 02c0000?02cffff sa45 0 0 1 0 1 1 0 1 128/64 05a0000?05bffff 02d0000?02dffff sa46 0 0 1 0 1 1 1 0 128/64 05c0000?05dffff 02e0000?02effff sa47 0 0 1 0 1 1 1 1 128/64 05e0000?05fffff 02f0000?02fffff sa48 0 0 1 1 0 0 0 0 128/64 0600000?061ffff 0300000?030ffff sa49 0 0 1 1 0 0 0 1 128/64 0620000?063ffff 0310000?031ffff sa50 0 0 1 1 0 0 1 0 128/64 0640000?065ffff 0320000?032ffff sa51 0 0 1 1 0 0 1 1 128/64 0660000?067ffff 0330000?033ffff sa52 0 0 1 1 0 1 0 0 128/64 0680000?069ffff 0340000?034ffff sa53 0 0 1 1 0 1 0 1 128/64 06a0000?06bffff 0350000?035ffff sa54 0 0 1 1 0 1 1 0 128/64 06c0000?06dffff 0360000?036ffff sa55 0 0 1 1 0 1 1 1 128/64 06e0000?06fffff 0370000?037ffff sa56 0 0 1 1 1 0 0 0 128/64 0700000?071ffff 0380000?038ffff sa57 0 0 1 1 1 0 0 1 128/64 0720000?073ffff 0390000?039ffff table 2. sector address table?s29gl256n (continued) sector a23?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
28 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information sa58 0 0 1 1 1 0 1 0 128/64 0740000?075ffff 03a0000?03affff sa59 0 0 1 1 1 0 1 1 128/64 0760000?077ffff 03b0000?03bffff sa60 0 0 1 1 1 1 0 0 128/64 0780000?079ffff 03c0000?03cffff sa61 0 0 1 1 1 1 0 1 128/64 07a0000?7bffff 03d0000?03dffff sa62 0 0 1 1 1 1 1 0 128/64 07c0000?07dffff 03e0000?03effff sa63 0 0 1 1 1 1 1 1 128/64 07e0000?07fffff0 03f0000?03fffff sa64 0 1 0 0 0 0 0 0 128/64 0800000?081ffff 0400000?040ffff sa65 0 1 0 0 0 0 0 1 128/64 0820000?083ffff 0410000?041ffff sa66 0 1 0 0 0 0 1 0 128/64 0840000?085ffff 0420000?042ffff sa67 0 1 0 0 0 0 1 1 128/64 0860000?087ffff 0430000?043ffff sa68 0 1 0 0 0 1 0 0 128/64 0880000?089ffff 0440000?044ffff sa69 0 1 0 0 0 1 0 1 128/64 08a0000?08bffff 0450000?045ffff sa70 0 1 0 0 0 1 1 0 128/64 08c0000?08dffff 0460000?046ffff sa71 0 1 0 0 0 1 1 1 128/64 08e0000?08fffff 0470000?047ffff sa72 0 1 0 0 1 0 0 0 128/64 0900000?091ffff 0480000?048ffff sa73 0 1 0 0 1 0 0 1 128/64 0920000?093ffff 0490000?049ffff sa74 0 1 0 0 1 0 1 0 128/64 0940000?095ffff 04a0000?04affff sa75 0 1 0 0 1 0 1 1 128/64 0960000?097ffff 04b0000?04bffff sa76 0 1 0 0 1 1 0 0 128/64 0980000?099ffff 04c0000?04cffff sa77 0 1 0 0 1 1 0 1 128/64 09a0000?09bffff 04d0000?04dffff sa78 0 1 0 0 1 1 1 0 128/64 09c0000?09dffff 04e0000?04effff sa79 0 1 0 0 1 1 1 1 128/64 09e0000?09fffff 04f0000?04fffff sa80 0 1 0 1 0 0 0 0 128/64 0a00000?0a1ffff 0500000?050ffff sa81 0 1 0 1 0 0 0 1 128/64 0a20000?0a3ffff 0510000?051ffff sa82 0 1 0 1 0 0 1 0 128/64 0a40000?045ffff 0520000?052ffff sa83 0 1 0 1 0 0 1 1 128/64 0a60000?0a7ffff 0530000?053ffff sa84 0 1 0 1 0 1 0 0 128/64 0a80000?0a9ffff 0540000?054ffff sa85 0 1 0 1 0 1 0 1 128/64 0aa0000?0abffff 0550000?055ffff sa86 0 1 0 1 0 1 1 0 128/64 0ac0000?0adffff 0560000?056ffff sa87 0 1 0 1 0 1 1 1 128/64 0ae0000?aefffff 0570000?057ffff sa88 0 1 0 1 1 0 0 0 128/64 0b00000?0b1ffff 0580000?058ffff sa89 0 1 0 1 1 0 0 1 128/64 0b20000?0b3ffff 0590000?059ffff sa90 0 1 0 1 1 0 1 0 128/64 0b40000?0b5ffff 05a0000?05affff sa91 0 1 0 1 1 0 1 1 128/64 0b60000?0b7ffff 05b0000?05bffff sa92 0 1 0 1 1 1 0 0 128/64 0b80000?0b9ffff 05c0000?05cffff table 2. sector address table?s29gl256n (continued) sector a23?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 29 advance information sa93 0 1 0 1 1 1 0 1 128/64 0ba0000?0bbffff 05d0000?05dffff sa94 0 1 0 1 1 1 1 0 128/64 0bc0000?0bdffff 05e0000?05effff sa95 0 1 0 1 1 1 1 1 128/64 0be0000?0bfffff 05f0000?05fffff sa96 0 1 1 0 0 0 0 0 128/64 0c00000?0c1ffff 0600000?060ffff sa97 0 1 1 0 0 0 0 1 128/64 0c20000?0c3ffff 0610000?061ffff sa98 0 1 1 0 0 0 1 0 128/64 0c40000?0c5ffff 0620000?062ffff sa99 0 1 1 0 0 0 1 1 128/64 0c60000?0c7ffff 0630000?063ffff sa100 0 1 1 0 0 1 0 0 128/64 0c80000?0c9ffff 0640000?064ffff sa101 0 1 1 0 0 1 0 1 128/64 0ca0000?0cbffff 0650000?065ffff sa102 0 1 1 0 0 1 1 0 128/64 0cc0000?0cdffff 0660000?066ffff sa103 0 1 1 0 0 1 1 1 128/64 0ce0000?0cfffff 0670000?067ffff sa104 0 1 1 0 1 0 0 0 128/64 0d00000?0d1ffff 0680000?068ffff sa105 0 1 1 0 1 0 0 1 128/64 0d20000?0d3ffff 0690000?069ffff sa106 0 1 1 0 1 0 1 0 128/64 0d40000?0d5ffff 06a0000?06affff sa107 0 1 1 0 1 0 1 1 128/64 0d60000?0d7ffff 06b0000?06bffff sa108 0 1 1 0 1 1 0 0 128/64 0d80000?0d9ffff 06c0000?06cffff sa109 0 1 1 0 1 1 0 1 128/64 0da0000?0dbffff 06d0000?06dffff sa110 0 1 1 0 1 1 1 0 128/64 0dc0000?0ddffff 06e0000?06effff sa111 0 1 1 0 1 1 1 1 128/64 0de0000?0dfffff 06f0000?06fffff sa112 0 1 1 1 0 0 0 0 128/64 0e00000?0e1ffff 0700000?070ffff sa113 0 1 1 1 0 0 0 1 128/64 0e20000?0e3ffff 0710000?071ffff sa114 0 1 1 1 0 0 1 0 128/64 0e40000?0e5ffff 0720000?072ffff sa115 0 1 1 1 0 0 1 1 128/64 0e60000?0e7ffff 0730000?073ffff sa116 0 1 1 1 0 1 0 0 128/64 0e80000?0e9ffff 0740000?074ffff sa117 0 1 1 1 0 1 0 1 128/64 0ea0000?0ebffff 0750000?075ffff sa118 0 1 1 1 0 1 1 0 128/64 0ec0000?0edffff 0760000?076ffff sa119 0 1 1 1 0 1 1 1 128/64 0ee0000?0efffff 0770000?077ffff sa120 0 1 1 1 1 0 0 0 128/64 0f00000?0f1ffff 0780000?078ffff sa121 0 1 1 1 1 0 0 1 128/64 0f20000?0f3ffff 0790000?079ffff sa122 0 1 1 1 1 0 1 0 128/64 0f40000?0f5ffff 07a0000?07affff sa123 0 1 1 1 1 0 1 1 128/64 0f60000?0f7ffff 07b0000?07bffff sa124 0 1 1 1 1 1 0 0 128/64 0f80000?0f9ffff 07c0000?07cffff sa125 0 1 1 1 1 1 0 1 128/64 0fa0000?0fbffff 07d0000?07dffff sa126 0 1 1 1 1 1 1 0 128/64 0fc0000?0fdffff 07e0000?07effff sa127 0 1 1 1 1 1 1 1 128/64 0fe0000?0ffffff 07f0000?07fffff table 2. sector address table?s29gl256n (continued) sector a23?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
30 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information sa128 1 0 0 0 0 0 0 0 128/64 1000000?101ffff 0800000?080ffff sa129 1 0 0 0 0 0 0 1 128/64 1020000?103ffff 0810000?081ffff sa130 1 0 0 0 0 0 1 0 128/64 1040000?105ffff 0820000?082ffff sa131 1 0 0 0 0 0 1 1 128/64 1060000?107ffff 0830000?083ffff sa132 1 0 0 0 0 1 0 0 128/64 1080000?109ffff 0840000?084ffff sa133 1 0 0 0 0 1 0 1 128/64 10a0000?10bffff 0850000?085ffff sa134 1 0 0 0 0 1 1 0 128/64 10c0000?10dffff 0860000?086ffff sa135 1 0 0 0 0 1 1 1 128/64 10e0000?10fffff 0870000?087ffff sa136 1 0 0 0 1 0 0 0 128/64 1100000?111ffff 0880000?088ffff sa137 1 0 0 0 1 0 0 1 128/64 1120000?113ffff 0890000?089ffff sa138 1 0 0 0 1 0 1 0 128/64 1140000?115ffff 08a0000?08affff sa139 1 0 0 0 1 0 1 1 128/64 1160000?117ffff 08b0000?08bffff sa140 1 0 0 0 1 1 0 0 128/64 1180000?119ffff 08c0000?08cffff sa141 1 0 0 0 1 1 0 1 128/64 11a0000?11bffff 08d0000?08dffff sa142 1 0 0 0 1 1 1 0 128/64 11c0000?11dffff 08e0000?08effff sa143 1 0 0 0 1 1 1 1 128/64 11e0000?11fffff 08f0000?08fffff sa144 1 0 0 1 0 0 0 0 128/64 1200000?121ffff 0900000?090ffff sa145 1 0 0 1 0 0 0 1 128/64 1220000?123ffff 0910000?091ffff sa146 1 0 0 1 0 0 1 0 128/64 1240000?125ffff 0920000?092ffff sa147 1 0 0 1 0 0 1 1 128/64 1260000?127ffff 0930000?093ffff sa148 1 0 0 1 0 1 0 0 128/64 1280000?129ffff 0940000?094ffff sa149 1 0 0 1 0 1 0 1 128/64 12a0000?12bffff 0950000?095ffff sa150 1 0 0 1 0 1 1 0 128/64 12c0000?12dffff 0960000?096ffff sa151 1 0 0 1 0 1 1 1 128/64 12e0000?12fffff 0970000?097ffff sa152 1 0 0 1 1 0 0 0 128/64 1300000?131ffff 0980000?098ffff sa153 1 0 0 1 1 0 0 1 128/64 1320000?133ffff 0990000?099ffff sa154 1 0 0 1 1 0 1 0 128/64 1340000?135ffff 09a0000?09affff sa155 1 0 0 1 1 0 1 1 128/64 1360000?137ffff 09b0000?09bffff sa156 1 0 0 1 1 1 0 0 128/64 1380000?139ffff 09c0000?09cffff sa157 1 0 0 1 1 1 0 1 128/64 13a0000?13bffff 09d0000?09dffff sa158 1 0 0 1 1 1 1 0 128/64 13c0000?13dffff 09e0000?09effff sa159 1 0 0 1 1 1 1 1 128/64 13e0000?13fffff 09f0000?09fffff sa160 1 0 1 0 0 0 0 0 128/64 1400000?141ffff 0a00000?0a0ffff sa161 1 0 1 0 0 0 0 1 128/64 1420000?143ffff 0a10000?0a1ffff sa162 1 0 1 0 0 0 1 0 128/64 1440000?145ffff 0a20000?0a2ffff table 2. sector address table?s29gl256n (continued) sector a23?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 31 advance information sa163 1 0 1 0 0 0 1 1 128/64 1460000?147ffff 0a30000?0a3ffff sa164 1 0 1 0 0 1 0 0 128/64 1480000?149ffff 0a40000?0a4ffff sa165 1 0 1 0 0 1 0 1 128/64 14a0000?14bffff 0a50000?0a5ffff sa166 1 0 1 0 0 1 1 0 128/64 14c0000?14dffff 0a60000?0a6ffff sa167 1 0 1 0 0 1 1 1 128/64 14e0000?14fffff 0a70000?0a7ffff sa168 1 0 1 0 1 0 0 0 128/64 1500000?151ffff 0a80000?0a8ffff sa169 1 0 1 0 1 0 0 1 128/64 1520000?153ffff 0a90000?0a9ffff sa170 1 0 1 0 1 0 1 0 128/64 1540000?155ffff 0aa0000?0aaffff sa171 1 0 1 0 1 0 1 1 128/64 1560000?157ffff 0ab0000?0abffff sa172 1 0 1 0 1 1 0 0 128/64 1580000?159ffff 0ac0000?0acffff sa173 1 0 1 0 1 1 0 1 128/64 15a0000?15bffff 0ad0000?0adffff sa174 1 0 1 0 1 1 1 0 128/64 15c0000?15dffff 0ae0000?0aeffff sa175 1 0 1 0 1 1 1 1 128/64 15e0000?15fffff 0af0000?0afffff sa176 1 0 1 1 0 0 0 0 128/64 1600000?161ffff 0b00000?0b0ffff sa177 1 0 1 1 0 0 0 1 128/64 1620000?163ffff 0b10000?0b1ffff sa178 1 0 1 1 0 0 1 0 128/64 1640000?165fffff 0b20000?0b2ffff sa179 1 0 1 1 0 0 1 1 128/64 1660000?167ffff 0b30000?0b3ffff sa180 1 0 1 1 0 1 0 0 128/64 1680000?169ffff 0b40000?0b4ffff sa181 1 0 1 1 0 1 0 1 128/64 16a0000?16bffff 0b50000?0b5ffff sa182 1 0 1 1 0 1 1 0 128/64 16c0000?16dffff 0b60000?0b6ffff sa183 1 0 1 1 0 1 1 1 128/64 16e0000?16fffff 0b70000?0b7ffff sa184 1 0 1 1 1 0 0 0 128/64 1700000?171ffff 0b80000?0b8ffff sa185 1 0 1 1 1 0 0 1 128/64 1720000?173ffff 0b90000?0b9ffff sa186 1 0 1 1 1 0 1 0 128/64 1740000?175ffff 0ba0000?0baffff sa187 1 0 1 1 1 0 1 1 128/64 1760000?177ffff 0bb0000?0bbffff sa188 1 0 1 1 1 1 0 0 128/64 1780000?179ffff 0bc0000?0bcffff sa189 1 0 1 1 1 1 0 1 128/64 17a0000?17bffff 0bd0000?0bdffff sa190 1 0 1 1 1 1 1 0 128/64 17c0000?17dffff 0be0000?0beffff sa191 1 0 1 1 1 1 1 1 128/64 17e0000?17fffff 0bf0000?0bfffff sa192 1 1 0 0 0 0 0 0 128/64 1800000?181ffff 0c00000?0c0ffff sa193 1 1 0 0 0 0 0 1 128/64 1820000?183ffff 0c10000?0c1ffff sa194 1 1 0 0 0 0 1 0 128/64 1840000?185ffff 0c20000?0c2ffff sa195 1 1 0 0 0 0 1 1 128/64 1860000?187ffff 0c30000?0c3ffff sa196 1 1 0 0 0 1 0 0 128/64 1880000?189ffff 0c40000?0c4ffff sa197 1 1 0 0 0 1 0 1 128/64 18a0000?18bffff 0c50000?0c5ffff table 2. sector address table?s29gl256n (continued) sector a23?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
32 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information sa198 1 1 0 0 0 1 1 0 128/64 18c0000?18dffff 0c60000?0c6ffff sa199 1 1 0 0 0 1 1 1 128/64 18e0000?18fffff 0c70000?0c7ffff sa200 1 1 0 0 1 0 0 0 128/64 1900000?191ffff 0c80000?0c8ffff sa201 1 1 0 0 1 0 0 1 128/64 1920000?193ffff 0c90000?0c9ffff sa202 1 1 0 0 1 0 1 0 128/64 1940000?195ffff 0ca0000?0caffff sa203 1 1 0 0 1 0 1 1 128/64 1960000?197ffff 0cb0000?0cbffff sa204 1 1 0 0 1 1 0 0 128/64 1980000?199ffff 0cc0000?0ccffff sa205 1 1 0 0 1 1 0 1 128/64 19a0000?19bffff 0cd0000?0cdffff sa206 1 1 0 0 1 1 1 0 128/64 19c0000?19dffff 0ce0000?0ceffff sa207 1 1 0 0 1 1 1 1 128/64 19e0000?19ffff 0cf0000?0cfffff sa208 1 1 0 1 0 0 0 0 128/64 1a00000?1a1ffff 0d00000?0d0ffff sa209 1 1 0 1 0 0 0 1 128/64 1a20000?1a3ffff 0d10000?0d1ffff sa210 1 1 0 1 0 0 1 0 128/64 1a40000?1a5ffff 0d20000?0d2ffff sa211 1 1 0 1 0 0 1 1 128/64 1a60000?1a7ffff 0d30000?0d3ffff sa212 1 1 0 1 0 1 0 0 128/64 1a80000?1a9ffff 0d40000?0d4ffff sa213 1 1 0 1 0 1 0 1 128/64 1aa0000?1abffff 0d50000?0d5ffff sa214 1 1 0 1 0 1 1 0 128/64 1ac0000?1adffff 0d60000?0d6ffff sa215 1 1 0 1 0 1 1 1 128/64 1ae0000?1afffff 0d70000?0d7ffff sa216 1 1 0 1 1 0 0 0 128/64 1b00000?1b1ffff 0d80000?0d8ffff sa217 1 1 0 1 1 0 0 1 128/64 1b20000?1b3ffff 0d90000?0d9ffff sa218 1 1 0 1 1 0 1 0 128/64 1b40000?1b5ffff 0da0000?0daffff sa219 1 1 0 1 1 0 1 1 128/64 1b60000?1b7ffff 0db0000?0dbffff sa220 1 1 0 1 1 1 0 0 128/64 1b80000?1b9ffff 0dc0000?0dcffff sa221 1 1 0 1 1 1 0 1 128/64 1ba0000?1bbffff 0dd0000?0ddffff sa222 1 1 0 1 1 1 1 0 128/64 1bc0000?1bdffff 0de0000?0deffff sa223 1 1 0 1 1 1 1 1 128/64 1be0000?1bfffff 0df0000?0dfffff sa224 1 1 1 0 0 0 0 0 128/64 1c00000?1c1ffff 0e00000?0e0ffff sa225 1 1 1 0 0 0 0 1 128/64 1c20000?1c3ffff 0e10000?0e1ffff sa226 1 1 1 0 0 0 1 0 128/64 1c40000?1c5ffff 0e20000?0e2ffff sa227 1 1 1 0 0 0 1 1 128/64 1c60000?1c7ffff 0e30000?0e3ffff sa228 1 1 1 0 0 1 0 0 128/64 1c80000?1c9ffff 0e40000?0e4ffff sa229 1 1 1 0 0 1 0 1 128/64 1ca0000?1cbffff 0e50000?0e5ffff sa230 1 1 1 0 0 1 1 0 128/64 1cc0000?1cdffff 0e60000?0e6ffff sa231 1 1 1 0 0 1 1 1 128/64 1ce0000?1cfffff 0e70000?0e7ffff sa232 1 1 1 0 1 0 0 0 128/64 1d00000?1d1ffff 0e80000?0e8ffff table 2. sector address table?s29gl256n (continued) sector a23?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 33 advance information sa233 1 1 1 0 1 0 0 1 128/64 1d20000?1d3ffff 0e90000?0e9ffff sa234 1 1 1 0 1 0 1 0 128/64 1d40000?1d5ffff 0ea0000?0eaffff sa235 1 1 1 0 1 0 1 1 128/64 1d60000?1d7ffff 0eb0000?0ebffff sa236 1 1 1 0 1 1 0 0 128/64 1d80000?1d9ffff 0ec0000?0ecffff sa237 1 1 1 0 1 1 0 1 128/64 1da0000?1dbffff 0ed0000?0edffff sa238 1 1 1 0 1 1 1 0 128/64 1dc0000?1ddffff 0ee0000?0eeffff sa239 1 1 1 0 1 1 1 1 128/64 1de0000?1dfffff 0ef0000?0efffff sa240 1 1 1 1 0 0 0 0 128/64 1e00000?1e1ffff 0f00000?0f0ffff sa241 1 1 1 1 0 0 0 1 128/64 1e20000?1e3ffff 0f10000?0f1ffff sa242 1 1 1 1 0 0 1 0 128/64 1e40000?1e5ffff 0f20000?0f2ffff sa243 1 1 1 1 0 0 1 1 128/64 1e60000?137ffff 0f30000?0f3ffff sa244 1 1 1 1 0 1 0 0 128/64 1e80000?1e9ffff 0f40000?0f4ffff sa245 1 1 1 1 0 1 0 1 128/64 1ea0000?1ebffff 0f50000?0f5ffff sa246 1 1 1 1 0 1 1 0 128/64 1ec0000?1edffff 0f60000?0f6ffff sa247 1 1 1 1 0 1 1 1 128/64 1ee0000?1efffff 0f70000?0f7ffff sa248 1 1 1 1 1 0 0 0 128/64 1f00000?1f1ffff 0f80000?0f8ffff sa249 1 1 1 1 1 0 0 1 128/64 1f20000?1f3ffff 0f90000?0f9ffff sa250 1 1 1 1 1 0 1 0 128/64 1f40000?1f5ffff 0fa0000?0faffff sa251 1 1 1 1 1 0 1 1 128/64 1f60000?1f7ffff 0fb0000?0fbffff sa252 1 1 1 1 1 1 0 0 128/64 1f80000?1f9ffff 0fc0000?0fcffff sa253 1 1 1 1 1 1 0 1 128/64 1fa0000?1fbffff 0fd0000?0fdffff sa254 1 1 1 1 1 1 1 0 128/64 1fc0000?1fdffff 0fe0000?0feffff sa255 1 1 1 1 1 1 1 1 128/64 1fe0000?1ffffff 0ff0000?0ffffff table 3. sector address table?s29gl128n sector a22?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) sa0 0 0 0 0 0 0 128/64 0000000?001ffff 0000000?000ffff sa1 0 0 0 0 0 1 128/64 0020000?003ffff 0010000?001ffff sa2 0 0 0 0 1 0 128/64 0040000?005ffff 0020000?002ffff sa3 0 0 0 0 1 1 128/64 0060000?007ffff 0030000?003ffff sa4 0 0 0 1 0 0 128/64 0080000?009ffff 0040000?004ffff sa5 0 0 0 1 0 1 128/64 00a0000?00bffff 0050000?005ffff sa6 0 0 0 1 1 0 128/64 00c0000?00dffff 0060000?006ffff table 2. sector address table?s29gl256n (continued) sector a23?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
34 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information sa7 0 0 0 1 1 1 128/64 00e0000?00fffff 0070000?007ffff sa8 0 0 1 0 0 0 128/64 0100000?011ffff 0080000?008ffff sa9 0 0 1 0 0 1 128/64 0120000?013ffff 0090000?009ffff sa10 0 0 1 0 1 0 128/64 0140000?015ffff 00a0000?00affff sa11 0 0 1 0 1 1 128/64 0160000?017ffff 00b0000?00bffff sa12 0 0 1 1 0 0 128/64 0180000?019ffff 00c0000?00cffff sa13 0 0 1 1 0 1 128/64 01a0000?01bffff 00d0000?00dffff sa14 0 0 1 1 1 0 128/64 01c0000?01dffff 00e0000?00effff sa15 0 0 1 1 1 1 128/64 01e0000?01fffff 00f0000?00fffff sa16 0 1 0 0 0 0 128/64 0200000?021ffff 0100000?010ffff sa17 0 1 0 0 0 1 128/64 0220000?023ffff 0110000?011ffff sa18 0 1 0 0 1 0 128/64 0240000?025ffff 0120000?012ffff sa19 0 1 0 0 1 1 128/64 0260000?027ffff 0130000?013ffff sa20 0 1 0 1 0 0 128/64 0280000?029ffff 0140000?014ffff sa21 0 1 0 1 0 1 128/64 02a0000?02bffff 0150000?015ffff sa22 0 1 0 1 1 0 128/64 02c0000?02dffff 0160000?016ffff sa23 0 1 0 1 1 1 128/64 02e0000?02fffff 0170000?017ffff sa24 0 1 1 0 0 0 128/64 0300000?031ffff 0180000?018ffff sa25 0 1 1 0 0 1 128/64 0320000?033ffff 0190000?019ffff sa26 0 1 1 0 1 0 128/64 0340000?035ffff 01a0000?01affff sa27 0 1 1 0 1 1 128/64 0360000?037ffff 01b0000?01bffff sa28 0 1 1 1 0 0 128/64 0380000?039ffff 01c0000?01cffff sa29 0 1 1 1 0 1 128/64 03a0000?03bffff 01d0000?01dffff sa30 0 1 1 1 1 0 128/64 03c0000?03dffff 01e0000?01effff sa31 0 1 1 1 1 1 128/64 03e0000?03fffff 01f0000?01fffff sa32 1 0 0 0 0 0 128/64 0400000?041ffff 0200000?020ffff sa33 1 0 0 0 0 1 128/64 0420000?043ffff 0210000?021ffff sa34 1 0 0 0 1 0 128/64 0440000?045ffff 0220000?022ffff sa35 1 0 0 0 1 1 128/64 0460000?047ffff 0230000?023ffff sa36 1 0 0 1 0 0 128/64 0480000?049ffff 0240000?024ffff sa37 1 0 0 1 0 1 128/64 04a0000?04bffff 0250000?025ffff sa38 1 0 0 1 1 0 128/64 04c0000?04dffff 0260000?026ffff sa39 1 0 0 1 1 1 128/64 04e0000?04fffff 0270000?027ffff sa40 1 0 1 0 0 0 128/64 0500000?051ffff 0280000?028ffff sa41 1 0 1 0 0 1 128/64 0520000?053ffff 0290000?029ffff table 3. sector address table?s29gl128n (continued) sector a22?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 35 advance information sa42 1 0 1 0 1 0 128/64 0540000?055ffff 02a0000?02affff sa43 1 0 1 0 1 1 128/64 0560000?057ffff 02b0000?02bffff sa44 1 0 1 1 0 0 128/64 0580000?059ffff 02c0000?02cffff sa45 1 0 1 1 0 1 128/64 05a0000?05bffff 02d0000?02dffff sa46 1 0 1 1 1 0 128/64 05c0000?05dffff 02e0000?02effff sa47 1 0 1 1 1 1 128/64 05e0000?05fffff 02f0000?02fffff sa48 1 1 0 0 0 0 128/64 0600000?061ffff 0300000?030ffff sa49 1 1 0 0 0 1 128/64 0620000?063ffff 0310000?031ffff sa50 1 1 0 0 1 0 128/64 0640000?065ffff 0320000?032ffff sa51 1 1 0 0 1 1 128/64 0660000?067ffff 0330000?033ffff sa52 1 1 0 1 0 0 128/64 0680000?069ffff 0340000?034ffff sa53 1 1 0 1 0 1 128/64 06a0000?06bffff 0350000?035ffff sa54 1 1 0 1 1 0 128/64 06c0000?06dffff 0360000?036ffff sa55 1 1 0 1 1 1 128/64 06e0000?06fffff 0370000?037ffff sa56 1 1 1 0 0 0 128/64 0700000?071ffff 0380000?038ffff sa57 1 1 1 0 0 1 128/64 0720000?073ffff 0390000?039ffff sa58 1 1 1 0 1 0 128/64 0740000?075ffff 03a0000?03affff sa59 1 1 1 0 1 1 128/64 0760000?077ffff 03b0000?03bffff sa60 1 1 1 1 0 0 128/64 0780000?079ffff 03c0000?03cffff sa61 1 1 1 1 0 1 128/64 07a0000?07bffff 03d0000?03dffff sa62 1 1 1 1 1 0 128/64 07c0000?07dffff 03e0000?03effff sa63 1 1 1 1 1 1 128/64 07e0000?07fffff 03f0000?03fffff sa64 0 0 0 0 0 0 128/64 0800000?081ffff 0400000?040ffff sa65 0 0 0 0 0 1 128/64 0820000?083ffff 0410000?041ffff sa66 0 0 0 0 1 0 128/64 0840000?085ffff 0420000?042ffff sa67 0 0 0 0 1 1 128/64 0860000?087ffff 0430000?043ffff sa68 0 0 0 1 0 0 128/64 0880000?089ffff 0440000?044ffff sa69 0 0 0 1 0 1 128/64 08a0000?08bffff 0450000?045ffff sa70 0 0 0 1 1 0 128/64 08c0000?08dffff 0460000?046ffff sa71 0 0 0 1 1 1 128/64 08e0000?08fffff 0470000?047ffff sa72 0 0 1 0 0 0 128/64 0900000?091ffff 0480000?048ffff sa73 0 0 1 0 0 1 128/64 0920000?093ffff 0490000?049ffff sa74 0 0 1 0 1 0 128/64 0940000?095ffff 04a0000?04affff sa75 0 0 1 0 1 1 128/64 0960000?097ffff 04b0000?04bffff sa76 0 0 1 1 0 0 128/64 0980000?099ffff 04c0000?04cffff table 3. sector address table?s29gl128n (continued) sector a22?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
36 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information sa77 0 0 1 1 0 1 128/64 09a0000?09bffff 04d0000?04dffff sa78 0 0 1 1 1 0 128/64 09c0000?09dffff 04e0000?04effff sa79 0 0 1 1 1 1 128/64 09e0000?09fffff 04f0000?04fffff sa80 0 1 0 0 0 0 128/64 0a00000?0a1ffff 0500000?050ffff sa81 0 1 0 0 0 1 128/64 0a20000?0a3ffff 0510000?051ffff sa82 0 1 0 0 1 0 128/64 0a40000?0a5ffff 0520000?052ffff sa83 0 1 0 0 1 1 128/64 0a60000?0a7ffff 0530000?053ffff sa84 0 1 0 1 0 0 128/64 0a80000?0a9ffff 0540000?054ffff sa85 0 1 0 1 0 1 128/64 0aa0000?0abffff 0550000?055ffff sa86 0 1 0 1 1 0 128/64 0ac0000?0adffff 0560000?056ffff sa87 0 1 0 1 1 1 128/64 0ae0000?0afffff 0570000?057ffff sa88 0 1 1 0 0 0 128/64 0b00000?0b1ffff 0580000?058ffff sa89 0 1 1 0 0 1 128/64 0b20000?0b3ffff 0590000?059ffff sa90 0 1 1 0 1 0 128/64 0b40000?0b5ffff 05a0000?05affff sa91 0 1 1 0 1 1 128/64 0b60000?0b7ffff 05b0000?05bffff sa92 0 1 1 1 0 0 128/64 0b80000?0b9ffff 05c0000?05cffff sa93 0 1 1 1 0 1 128/64 0ba0000?0bbffff 05d0000?05dffff sa94 0 1 1 1 1 0 128/64 0bc0000?0bdffff 05e0000?05effff sa95 0 1 1 1 1 1 128/64 0be0000?0bfffff 05f0000?05fffff sa96 1 0 0 0 0 0 128/64 0c00000?0c1ffff 0600000?060ffff sa97 1 0 0 0 0 1 128/64 0c20000?0c3ffff 0610000?061ffff sa98 1 0 0 0 1 0 128/64 0c40000?0c5ffff 0620000?062ffff sa99 1 0 0 0 1 1 128/64 0c60000?0c7ffff 0630000?063ffff sa100 1 0 0 1 0 0 128/64 0c80000?0c9ffff 0640000?064ffff sa101 1 0 0 1 0 1 128/64 0ca0000?0cbffff 0650000?065ffff sa102 1 0 0 1 1 0 128/64 0cc0000?0cdffff 0660000?066ffff sa103 1 0 0 1 1 1 128/64 0ce0000?0cfffff 0670000?067ffff sa104 1 0 1 0 0 0 128/64 0d00000?0d1ffff 0680000?068ffff sa105 1 0 1 0 0 1 128/64 0d20000?0d3ffff 0690000?069ffff sa106 1 0 1 0 1 0 128/64 0d40000?0d5ffff 06a0000?06affff sa107 1 0 1 0 1 1 128/64 0d60000?0d7ffff 06b0000?06bffff sa108 1 0 1 1 0 0 128/64 0d80000?0d9ffff 06c0000?06cffff sa109 1 0 1 1 0 1 128/64 0da0000?0dbffff 06d0000?06dffff sa110 1 0 1 1 1 0 128/64 0dc0000?0ddffff 06e0000?06effff sa111 1 0 1 1 1 1 128/64 0de0000?0dfffff 06f0000?06fffff table 3. sector address table?s29gl128n (continued) sector a22?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 37 advance information sector protection the device features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: persistent sector protection a command sector protection method that replaces the old 12 v controlled pro- tection method. password sector protection a highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted wp# hardware protection a write protect pin that can prevent program or erase operations in the outermost sectors. the wp# hardware protection feature is always available, independent of the software managed protection method chosen. selecting a sector protection mode all parts default to operate in the persistent sector protection mode. the cus- tomer must then choose if the persistent or password protection method is most desirable. there are two one-time programmable non-volatile bits that define which sector protection method will be used. if the customer decides to continue using the persistent sector protection method, they must set the persistent sector protection mode locking bit . this will permanently set the part to op- sa112 1 1 0 0 0 0 128/64 0e00000?0e1ffff 0700000?070ffff sa113 1 1 0 0 0 1 128/64 0e20000?0e3ffff 0710000?071ffff sa114 1 1 0 0 1 0 128/64 0e40000?0e5ffff 0720000?072ffff sa115 1 1 0 0 1 1 128/64 0e60000?0e7ffff 0730000?073ffff sa116 1 1 0 1 0 0 128/64 0e80000?0e9ffff 0740000?074ffff sa117 1 1 0 1 0 1 128/64 0ea0000?0ebffff 0750000?075ffff sa118 1 1 0 1 1 0 128/64 0ec0000?0edffff 0760000?076ffff sa119 1 1 0 1 1 1 128/64 0ee0000?0efffff 0770000?077ffff sa120 1 1 1 0 0 0 128/64 0f00000?0f1ffff 0780000?078ffff sa121 1 1 1 0 0 1 128/64 0f20000?0f3ffff 0790000?079ffff sa122 1 1 1 0 1 0 128/64 0f40000?0f5ffff 07a0000?07affff sa123 1 1 1 0 1 1 128/64 0f60000?0f7ffff 07b0000?07bffff sa124 1 1 1 1 0 0 128/64 0f80000?0f9ffff 07c0000?07cffff sa125 1 1 1 1 0 1 128/64 0fa0000?0fbffff 07d0000?07dffff sa126 1 1 1 1 1 0 128/64 0fc0000?0fdffff 07e0000?07effff sa127 1 1 1 1 1 1 128/64 0fe0000?0ffffff 07f0000?07fffff table 3. sector address table?s29gl128n (continued) sector a22?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
38 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information erate only using persistent sector protection. if the customer decides to use the password method, they must set the password mode locking bit . this will permanently set the part to operate only using password sector protection. it is important to remember that setting either the persistent sector protec- tion mode locking bit or the password mode locking bit permanently selects the protection mode. it is not possible to switch between the two methods once a locking bit has been set. it is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. this is so that it is not possible for a system program or virus to later set the password mode locking bit, which would cause an unex- pected shift from the default persistent sector protection mode into the password protection mode. the device is shipped with all sectors unprotected. the factory offers the option of programming and protecting sectors at the factory prior to shipping the device through the expressflash? service. contact your sales representative for details. it is possible to determine whether a sector is protected or unprotected. see ?au- toselect command sequence? section on page 50 for details. advanced sector protection advanced sector protection features several levels of sector protection, which can disable both the program and erase operations in certain sectors. persistent sector protection is a method that replaces the old 12v controlled protection method. password sector protection is a highly sophisticated protection method that requires a password before changes to certain sectors are permitted. advanced sector protection is available when acc = v hh . lock register the lock register consists of 3 bits (dq2, dq1, and dq0). these dq2, dq1, dq0 bits of the lock register are programmable by the user. users are not allowed to program both dq2 and dq1 bits of the lock register to the 00 state. if the user tries to program dq2 and dq1 bits of the lock register to the 00 state, the device will abort the lock register back to the default 11 state. the programming time of the lock register is same as the typical word programming time without uti- lizing the write buffer of the device. during a lock register programming sequence execution, the dq6 toggle bit i will toggle until the programming of the lock register has completed to indicate programming status. all lock register bits are readable to allow users to verify lock register statuses. initial access delay is required to read the lock register. the customer secured silicon sector protection bit is dq0, persistent protection mode lock bit is dq1, and password protection mode lock bit is dq2 are acces- sible by all users. each of these bits are non-volatile. dq15-dq3 are reserved and must be 1's when the user tries to program the dq2, dq1, and dq0 bits of the lock register. the user is not required to program dq2, dq1 and dq0 bits of the lock register at the same time. this allows users to lock the secured silicon sec- tor and then set the device either permanently into password protection mode or persistent protection mode and then lock the secured silicon sector at separate instances and time frames. ? secured silicon sector protection allows the user to lock the secured silicon sector area
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 39 advance information ? persistent protection mode lock bit allows the user to set the device perma- nently to operate in the persistent protection mode ? password protection mode lock bit allows the user to set the device perma- nently to operate in the password protection mode ta b l e 4 . lock register persistent sector protection the persistent sector protection method replaces the old 12 v controlled protec- tion method while at the same time enhancing flexibility by providing three different sector protection states: ? dynamically locked -the sector is protected and can be changed by a sim- ple command ? persistently locked -a sector is protected and cannot be changed ? unlocked -the sector is unprotected and can be changed by a simple com- mand in order to achieve these states, three types of ?bits? are going to be used: dynamic protection bit (dyb) a volatile protection bit is assigned for each sector. after power-up or hardware reset, the contents of all dyb bits are in the ?unprotected state? if the dyb lock bit of the ?lock register? is not programmed. if the dyb lock bit of the ?lock register? is programmed, all dyb bits will power-up or hardware reset to the ?protected state?. each dyb is individually modifiable through the dyb set com- mand and dyb clear command. when the parts are first shipped, all of the persistent protect bits (ppb) are cleared into the unprotected state. the dyb bits and ppb lock bit are defaulted to power up in the cleared state or unprotected state - meaning the all ppb bits are changeable. the protection state for each sector is determined by the logical or of the ppb and the dyb related to that sector. for the sectors that have the ppb bits cleared, the dyb bits control whether or not the sector is protected or unprotected. by is- suing the dyb set and dyb clear command sequences, the dyb bits will be protected or unprotected, thus placing each sector in the protected or unpro- tected state. these are the so-called dynamic locked or unlocked states. they are called dynamic states because it is very easy to switch back and forth be- tween the protected and un-protected conditions. this allows software to easily protect sectors against inadvertent changes yet does not prevent the easy re- moval of protection when changes are needed. the dyb bits maybe set or cleared as often as needed. the ppb bits allow for a more static, and difficult to change, level of protection. the ppb bits retain their state across power cycles because they are non-volatile. individual ppb bits are set with a program command but must all be cleared as a group through an erase command. the ppb lock bit adds an additional level of protection. once all ppb bits are pro- grammed to the desired settings, the ppb lock bit may be set to the ?freeze dq15-3 dq2 dq1 dq0 don?t care password protection mode lock bit persistent protection mode lock bit secured silicon sector protection bit
40 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information state?. setting the ppb lock bit to the ?freeze state? disables all program and erase commands to the non-volatile ppb bits. in effect, the ppb lock bit locks the ppb bits into their current state. the only way to clear the ppb lock bit to the ?unfreeze state? is to go through a power cycle, or hardware reset. the software reset command will not clear the ppb lock bit to the ?unfreeze state?. system boot code can determine if any changes to the ppb bits are needed e.g. to allow new system code to be downloaded. if no changes are needed then the boot code can set the ppb lock bit to disable any further changes to the ppb bits during system operation. the wp# write protect pin adds a final level of hardware protection. when this pin is low it is not possible to change the contents of the wp# protected sectors. these sectors generally hold system boot code. so, the wp# pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. it is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. the sectors in the dynamic state are all unprotected. if there is a need to protect some of them, a simple dyb set command sequence is all that is necessary. the dyb set and dyb clear commands for the dynamic sectors switch the dyb bits to signify protected and unprotected, respectively. if there is a need to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bit must be disabled to the ?unfreeze state? by either putting the device through a power-cycle, or hardware reset. the ppb bits can then be changed to reflect the desired settings. setting the ppb lock bit once again to the ?freeze state? will lock the ppb bits, and the device operates normally again. note: to achieve the best protection, it's recommended to execute the ppb lock bit set command early in the boot code, and protect the boot code by holding wp# = v il . persistent protection bit (ppb) a single persistent (non-volatile) protection bit is assigned to each sector. if a ppb is programmed to the protected state through the ?ppb program? command, that sector will be protected from program or erase operations will be read-only. if a ppb requires erasure, all of the sector ppb bits must first be erased in parallel through the ?all ppb erase? command. the ?all ppb erase? command will prepro- grammed all ppb bits prior to ppb erasing. all ppb bits erase in parallel, unlike programming where individual ppb bits are programmable. the ppb bits have the same endurance as the flash memory. programming the ppb bit requires the typical word programming time without uti- lizing the write buffer. during a ppb bit programming and a11 ppb bit erasing sequence execution, the dq6 toggle bit i will toggle until the programming of the ppb bit or erasing of all ppb bits has completed to indicate programming and erasing status. erasing all of the ppb bits at once requires typical sector erase time. during the erasing of all ppb bits, the dq3 sector erase timer bit will output a 1 to indicate the erasure of all ppb bits are in progress. when the erasure of all ppb bits has completed, the dq3 sector erase timer bit will output a 0 to indicate that all ppb bits have been erased. reading the ppb status bit requires the initial access time of the device.
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 41 advance information persistent protection bit lock (ppb lock bit) a global volatile bit. when set to the ?freeze state?, the ppb bits cannot be changed. when cleared to the ?unfreeze state?, the ppb bits are changeable. there is only one ppb lock bit per device. the ppb lock bit is cleared to the ?un- freeze state? after power-up or hardware reset. there is no command sequence to unlock or ?unfreeze? the ppb lock bit. configuring the ppb lock bit to the freeze state requires approximately 100ns. reading the ppb lock status bit requires the initial access time of the device. ta b l e 5 . sector protection schemes table 7 contains all possible combinations of the dyb bit, ppb bit, and ppb lock bit relating to the status of the sector. in summary, if the ppb bit is set, and the ppb lock bit is set, the sector is protected and the protection cannot be removed until the next power cycle or hardware reset clears the ppb lock bit to ?unfreeze state?. if the ppb bit is cleared, the sector can be dynamically locked or unlocked. the dyb bit then controls whether or not the sector is protected or unprotected. if the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. a program command to a protected sec- tor enables status polling for approximately 1 s before the device returns to read mode without having modified the contents of the protected sector. an erase command to a protected sector enables status polling for approximately 50 s after which the device returns to read mode without having erased the protected sector. the programming of the dyb bit, ppb bit, and ppb lock bit for a given sec- tor can be verified by writing a dyb status read, ppb status read, and ppb lock status read commands to the device. the autoselect sector protection verification outputs the or function of the dyb bit and ppb bit per sector basis. when the or function of the dyb bit and ppb bit is a 1, the sector is either protected by dyb or ppb or both. when the or function of the dyb bit and ppb bit is a 0, the sector is unprotected through both the dyb and ppb. persistent protection mode lock bit like the password protection mode lock bit, a persistent protection mode lock bit exists to guarantee that the device remain in software sector protection. once programmed, the persistent protection mode lock bit prevents programming of protection states sector state dyb bit ppb bit ppb lock bit unprotect unprotect unfreeze unprotected ? ppb and dyb are changeable unprotect unprotect freeze unprotected ? ppb not changeable, dyb is changeable unprotect protect unfreeze protected ? ppb and dyb are changeable unprotect protect freeze protected ? ppb not changeable, dyb is changeable protect unprotect unfreeze protected ? ppb and dyb are changeable protect unprotect freeze protected ? ppb not changeable, dyb is changeable protect protect unfreeze protected ? ppb and dyb are changeable protect protect freeze protected ? ppb not changeable, dyb is changeable
42 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information the password protection mode lock bit. this guarantees that a hacker could not place the device in password protection mode. the password protection mode lock bit resides in the ?lock register?. password sector protection the password sector protection method allows an even higher level of security than the persistent sector protection method. there are two main differences be- tween the persistent sector protection and the password sector protection methods: ? when the device is first powered on, or comes out of a reset cycle, the ppb lock bit is set to the locked state, or the freeze state, rather than cleared to the unlocked state, or the unfreeze state. ? the only means to clear and unfreeze the ppb lock bit is by writing a unique 64-bit password to the device. the password sector protection method is otherwise identical to the persistent sector protection method. a 64-bit password is the only additional tool utilized in this method. the password is stored in a one-time programmable (otp) region outside of the flash memory. once the password protection mode lock bit is set, the password is permanently set with no means to read, program, or erase it. the password is used to clear and unfreeze the ppb lock bit. the password unlock command must be written to the flash, along with a password. the flash device internally com- pares the given password with the pre-programmed password. if they match, the ppb lock bit is cleared to the ?unfreezed state?, and the ppb bits can be altered. if they do not match, the flash device does nothing. there is a built-in 2 s delay for each ?password check? after the valid 64-bit password has been entered for the ppb lock bit to be cleared to the ?unfreezed state?. this delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. password and password protection mode lock bit in order to select the password sector protection method, the customer must first program the password. the factory recommends that the password be somehow correlated to the unique electronic serial number (esn) of the particular flash de- vice. each esn is different for every flash device; therefore each password should be different for every flash device. while programming in the password region, the customer may perform password read operations. once the desired pass- word is programmed in, the customer must then set the password protection mode lock bit. this operation achieves two objectives: 1. it permanently sets the device to operate using the password protection mode. it is not possible to reverse this function. 2. it also disables all further commands to the password region. all program, and read operations are ignored. both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. the user must be sure that the password sector protec- tion method is desired when programming the password protection mode lock bit. more importantly, the user must be sure that the password is correct when the password protection mode lock bit is programmed. due to the fact that read operations are disabled, there is no means to read what the password is after- wards. if the password is lost after programming the password protection mode
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 43 advance information lock bit, there will be no way to clear and unfreeze the ppb lock bit. the pass- word protection mode lock bit, once programmed, prevents reading the 64-bit password on the dq bus and further password programming. the password pro- tection mode lock bit is not erasable. once password protection mode lock bit is programmed, the persistent protection mode lock bit is disabled from program- ming, guaranteeing that no changes to the protection scheme are allowed. 64-bit password the 64-bit password is located in its own memory space and is accessible through the use of the password program and password read commands. the password function works in conjunction with the password protection mode lock bit, which when programmed, prevents the password read command from reading the con- tents of the password on the pins of the device. persistent protection bit lock (ppb lock bit) a global volatile bit. the ppb lock bit is a volatile bit that reflects the state of the password protection mode lock bit after power-up reset. if the password protec- tion mode lock bit is also programmed after programming the password, the password unlock command must be issued to clear and unfreeze the ppb lock bit after a hardware reset (reset# asserted) or a power-up reset. successful exe- cution of the password unlock command clears and unfreezes the ppb lock bit, allowing for sector ppb bits to be modified. without issuing the password unlock command, while asserting reset#, taking the device through a power-on reset, or issuing the ppb lock bit set command sets the ppb lock bit to a the ?freeze state?. if the password protection mode lock bit is not programmed, the device defaults to persistent protection mode. in the persistent protection mode, the ppb lock bit is cleared to the ?unfreeze state? after power-up or hardware reset. the ppb lock bit is set to the ?freeze state? by issuing the ppb lock bit set command. once set to the ?freeze state? the only means for clearing the ppb lock bit to the ?unfreeze state? is by issuing a hardware or power-up reset. the password unlock com- mand is ignored in persistent protection mode. reading the ppb lock bit requires a 200ns access time. secured silicon sector flash memory region the secured silicon sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secured silicon sector is 256 bytes in length, and uses a secured silicon sector indicator bit (dq7) to indicate whether or not the secured silicon sector is locked when shipped from the factory. this bit is permanently set at the factory and can- not be changed, which prevents cloning of a factory locked part. this ensures the security of the esn once the product is shipped to the field. the factory offers the device with the secured silicon sector either customer lockable (standard shipping option) or factory locked (contact an amd sales rep- resentative for ordering information). the customer-lockable version is shipped with the secured silicon sector unprotected, allowing customers to program the sector after receiving the device. the customer-lockable version also has the se- cured silicon sector indicator bit permanently set to a ?0.? the factory-locked version is always protected when shipped from the factory, and has the secured silicon sector indicator bit permanently set to a ?1.? thus, the secured silicon sector indicator bit prevents customer-lockable devices from being used to re-
44 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information place devices that are factory locked. note that the acc function and unlock bypass modes are not available when the secured silicon sector is enabled. the secured silicon sector address space in this device is allocated as follows: the system accesses the secured silicon sector through a command sequence (see ?write protect (wp#)?). after the system has written the enter secured sil- icon sector command sequence, it may read the secured silicon sector by using the addresses normally occupied by the first sector (sa0). this mode of operation continues until the system issues the exit secured silicon sector command se- quence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to sector sa0. customer lockable: secured silicon sector not programmed or protected at the factory unless otherwise specified, the device is shipped such that the customer may program and protect the 256-byte secured silicon sector. the system may program the secured silicon sector using the write-buffer, ac- celerated and/or unlock bypass methods, in addition to the standard programming command sequence. see command definitions. programming and protecting the secured silicon sector must be used with cau- tion since, once protected, there is no procedure available for unprotecting the secured silicon sector area and none of the bits in the secured silicon sector memory space can be modified in any way. the secured silicon sector area can be protected using one of the following procedures: ? write the three-cycle enter secured silicon sector region command se- quence, and then follow the in-system sector protect algorithm as shown in figure 2 , except that reset# may be at either v ih or v id . this allows in-sys- tem protection of the secured silicon sector without raising any device pin to a high voltage. note that this method is only applicable to the secured silicon sector. ? to verify the protect/unprotect status of the secured silicon sector, follow the algorithm shown in figure 1 . once the secured silicon sector is programmed, locked and verified, the system must write the exit secured silicon sector region command sequence to return to reading and writing within the remainder of the array. factory locked: secured silicon sector programmed and protected at the factory in devices with an esn, the secured sili con sector is protected when the device is shipped from the factory. the secured silicon sector cannot be modified in any way. an esn factory locked device has an 16-byte random esn at addresses 000000h?000007h. please contact your sales representative for details on order- ing esn factory locked devices. customers may opt to have their code programmed by the factory through the expressflash service (express flash factory locked). the devices are then secured silicon sector address range customer lockable esn factory locked expressflash factory locked 000000h?000007h determined by customer esn esn or determined by customer 000008h?00007fh unavailable determined by customer
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 45 advance information shipped from the factory with the secured silicon sector permanently locked. contact your sales representative for details on using the expressflash service. write protect (wp#) the write protect function provides a hardware method of protecting the first or last sector group without using v id . write protect is one of two functions provided by the wp#/acc input. if the system asserts v il on the wp#/acc pin, the device disables program and erase functions in the first or last sector group independently of whether those sector groups were protected or unprotected using the method described in?ad- vanced sector protection? section on page 38. note that if wp#/acc is at v il when the device is in the standby mode, the maximum input load current is in- creased. see the table in ?dc characteristics? section on page 78. if the system asserts v ih on the wp#/acc pin, the device reverts to whether the first or last sector was previously set to be protected or un- protected using the method described in ?sector group protection and unprotection?. note that wp# has an internal pullup; when uncon- nected, wp# is at v ih . hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to tables 16 and 17 for command definitions). in addition, the following hardware data protection mea- sures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this pro- tects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up. common flash memory interface (cfi)
46 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information the common flash interface (cfi) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified soft- ware algorithms to be used for entire families of devices. software support can then be device-independent, jedec id-independent, and forward- and back- ward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h, any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 8-11. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the au- toselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 8?11. the system must write the reset command to return the device to reading array data. for further information, please refer to the cfi specification and cfi publication 100, available via the world wide web at http://www.amd.com/flash/cfi. alter- natively, contact your sales representative for copies of these documents.
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 47 advance information ta b l e 6 . cfi query identification string table 7. system interface string addresses (x16) data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) addresses (x16) data description 1bh 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0007h typical timeout per single byte/word write 2 n s 20h 0007h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 000ah typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0001h max. timeout for byte/word write 2 n times typical 24h 0005h max. timeout for buffer write 2 n times typical 25h 0004h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
48 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information ta b l e 8 . device geometry definition addresses (x16) data description 27h 001ah 0019h 0018h device size = 2 n byte 1a = 512 mb, 19 = 256 mb, 18 = 128 mb 28h 29h 0002h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 0005h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 0001h number of erase block regions within de vice (01h = uniform device, 02h = boot device) 2dh 2eh 2fh 30h 00xxh 000xh 0000h 000xh erase block region 1 information (refer to the cfi specification or cfi publication 100) 00ffh, 001h, 0000h, 0002h = 512 mb 00ffh, 0000h, 0000h, 0002h = 256 mb 007fh, 0000h, 0000h, 0002h = 128 mb 31h 32h 33h 34h 0000h 0000h 0000h 0000h erase block region 2 information (refer to cfi publication 100) 35h 36h 37h 38h 0000h 0000h 0000h 0000h erase block region 3 information (refer to cfi publication 100) 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information (refer to cfi publication 100)
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 49 advance information ta b l e 9 . primary vendor-specific extended query command definitions writing specific address and data commands or sequences into the command register initiates device operations. table 10 and table 11 define the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. a reset com- mand is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the ac characteristics section for timing diagrams. addresses (x16) data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii 44h 0033h minor version number, ascii 45h 0010h address sensitive unlock (bits 1-0) 0 = required, 1 = not required process technology (bits 7-2) 0100b = 110 nm mirrorbit 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 0008h sector protect/unprotect scheme 0008h = advanced sector protection 4ah 0000h simultaneous operation 00 = not supported, x = number of sectors in bank 4bh 0000h burst mode type 00 = not supported, 01 = supported 4ch 0002h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 0004h/ 0005h top/bottom boot sector flag 00h = uniform device without wp# protect, 02h = bottom boot device, 03h = top boot device, 04h = uniform sectors bottom wp# protect, 05h = uniform sectors top wp# protect 50h 0001h program suspend 00h = not supported, 01h = supported
50 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non- erase-suspended sector. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same ex- ception. see the erase suspend/erase resume commands section for more information. the system must issue the reset command to return the device to the read (or erase-suspend-read) mode if dq5 goes hi gh during an active program or erase operation, or if the device is in the autoselect mode. see the next section, reset command, for more information. see also requirements for reading array data in the device bus operations sec- tion for more information. the read-only operations??ac characteristics? section on page 80 provides the read parameters, and figure 11 shows the timing diagram. reset command writing the reset command resets the device to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to the read mode. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to the read mode. if the program command sequence is written while the device is in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. once programming begins, however, the device ig- nores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if the device entered the autoselect mode while in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in erase suspend). note that if dq1 goes high during a write buffer programming operation, the sys- tem must write the write-to-buffer-abort reset command sequence to reset the device for the next operation. autoselect command sequence the autoselect command sequence allows the host system to access the manu- facturer and device codes, and determine whether or not a sector is protected. ta b l e 10 and table 11 show the address and data requirements. this method re- quires v id on address pin a9. the autoselect command sequence may be written
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 51 advance information to an address that is either in the read or erase-suspend-read mode. the autose- lect command may not be written while the device is actively programming or erasing. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the autoselect command. the device then enters the autoselect mode. the system may read at any address any number of times without initiating another autoselect command sequence: ? a read cycle at address xx00h returns the manufacturer code. ? three read cycles at addresses 01h, 0eh, and 0fh return the device code. ? a read cycle to an address containing a sector address (sa), and the address 02h on a7?a0 in word mode returns 01h if the sector is protected, or 00h if it is unprotected. the system must write the reset command to return to the read mode (or erase- suspend-read mode if the device was previously in erase suspend). enter secured silicon sector/exit secured silicon sector command sequence the secured silicon sector region provides a secured data area containing an 8- word/16-byte random electronic serial number (esn). the system can access the secured silicon sector region by issuing the three-cycle enter secured silicon sector command sequence. the device continues to access the secured silicon sector region until the system issues the four-cycle exit secured silicon sector command sequence. the exit secured silicon sector command sequence returns the device to normal operation. table 10 and table 11 show the address and data requirements for both command sequences. see also ?secured silicon sector flash memory region? for further information. note that the acc function and un- lock bypass modes are not available when the secured silicon sector is enabled. word program command sequence programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up com- mand. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further con- trols or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. table 10 and table 11 show the address and data requirements for the word program command sequence. when the embedded program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. the system can determine the status of the program operation by using dq7 or dq6. refer to the write op- eration status section for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that the secured silicon sector, autoselect, and cfi functions are unavailable when a program operation is in progress. note that a hardware reset immediately terminates the program operation. the pro- gram command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. program- ming to the same word address multiple times without intervening erases is limited. for such application requirements, please contact your local spansion representative. any word cannot be programmed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and
52 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information dq6 status bits to indicate the operation was successful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass program com- mand sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. table 10 and table 11 show the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock by- pass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. (see table 10 and table 11 ). write buffer programming write buffer programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. this results in faster effective programming time than the standard programming algorithms. the write buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load command written at the sector address in which programming will occur. the fourth cycle writes the sec- tor address and the number of word locations, minus one, to be programmed. for example, if the system will program 6 unique address locations, then 05h should be written to the device. this tells the device how many write buffer addresses will be loaded with data and therefore when to expect the program buffer to flash command. the number of locations to program cannot exceed the size of the write buffer or the operation will abort. the fifth cycle writes the first address location and data to be programmed. the write-buffer-page is selected by address bits a max ?a 4 . all subsequent address/ data pairs must fall within the selected-write-buffer-page. the system then writes the remaining address/data pairs into the write buffer. write buffer loca- tions may be loaded in any order. the write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (this means write buffer programming cannot be performed across multiple write-buffer pages. this also means that write buffer program- ming cannot be performed across multiple sectors. if the system attempts to load programming data outside of the selected write-buffer page, the operation will abort.) note that if a write buffer address location is loaded multiple times, the address/ data pair counter will be decremented for every data load operation. the host system must therefore account for loadin g a write-buffer location more than once. the counter decrements for each data load operation, not for each unique write-buffer-address location. note also that if an address location is loaded more
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 53 advance information than once into the buffer, the final data loaded for that address will be programmed. once the specified number of write buffer locations have been loaded, the system must then write the program buffer to flash command at the sector address. any other address and data combination aborts the write buffer programming oper- ation. the device then begins programming. data polling should be used while monitoring the last address location loaded into the write buffer. dq7, dq6, dq5, and dq1 should be monitored to determine the device status during write buffer programming. the write-buffer programming operation can be suspended using the standard program suspend/resume commands. upon successful completion of the write buffer programming operation, the device is ready to execute the next command. the write buffer programming sequence can be aborted in the following ways: ? load a value that is greater than the page buffer size during the number of locations to program step. ? write to an address in a sector different than the one specified during the write-buffer-load command. ? write an address/data pair to a different write-buffer-page than the one se- lected by the starting address during the write buffer data loading stage of the operation. ? write data other than the confirm command after the specified number of data load cycles. the abort condition is indicated by dq1 = 1, dq7 = data# (for the last address location loaded), dq6 = toggle, and dq5=0. a write-to-buffer-abort reset com- mand sequence must be written to reset the device for the next operation. note that the full 3-cycle write-to-buffer-abort reset command sequence is required when using write-buffer-programming features in unlock bypass mode. write buffer programming is allowed in any sequence. note that the secured sil- icon sector, autoselect, and cfi functions are unavailable when a program operation is in progress. this flash device is capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. for applications requiring an excessive number of such re- peated write buffer programming operations, please contact your local spansion representative. any bit in a write buffer address range cannot be pro- grammed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was successful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? accelerated program the device offers accelerated program operations through the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, the device automatically en- ters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the wp#/acc pin to accelerate the operation. note that the wp#/ acc pin must not be at v hh for operations other than accelerated programming, or device damage may result. wp# has an internal pullup; when unconnected, wp# is at v ih . figure 3 illustrates the algorithm for the program operation. refer to the erase and program operations??ac characteristics? section on page 80 section for pa- rameters, and figure 14 for timing diagrams.
54 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information figure 1. write buffer programming operation write ?write to buffer? command and sector address write number of addresses to program minus 1(wc = 31) and sector address write program buffer to flash sector address write first address/data write to a different sector address fail or abort pa s s read dq15 - dq0 at last loaded address read dq15 - dq0 with address = last loaded address write next address/data pair wc = wc - 1 wc = 0 ? part of ?write to buffer? command sequence ye s ye s ye s ye s ye s ye s no no no no no no abort write to buffer operation? dq7 = data? dq7 = data? dq5 = 1? dq1 = 1? write to buffer aborted. must write ?write-to-buffer abort reset? command sequence to return to read mode. notes: 1. when sector address is specified, any address in the selected sector is acceptable. however, when loading write-buffer address locations with data, all addresses must fall within the selected write-buffer page. 2. dq7 may change simultaneously with dq5. therefore, dq7 should be verified. 3. if this flowchart location was reached because dq5= ?1?, then the device failed. if this flowchart location was reached because dq1= ?1?, then the write to buffer operation was aborted. in either case, the proper reset command must be written before the device can begin another operation. if dq1=1, write the write- buffer-programming-abort-reset command. if dq5=1, write the reset command. 4. see tables 16 and 17 for command sequences required for write buffer programming.
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 55 advance information figure 2. program operation program suspend/program resume command sequence the program suspend command allows the system to interrupt a programming operation or a write to buffer programming operation so that data can be read from any non-suspended sector. when th e program suspend command is written during a programming process, the device halts the program operation within 15 s maximum (5 s typical) and updates the status bits. addresses are not re- quired when writing the program suspend command. after the programming operation has been suspended, the system can read array data from any non-suspended sector. the program suspend command may also be issued during a programming operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the secured silicon sector area (one-time pro- gram area), then user must use the prop er command sequences to enter and exit this region. the system may also write the autoselect command sequence when the device is in the program suspend mode. the system can read as many autoselect codes as required. when the device exits the autoselect mode, the device reverts to the program suspend mode, and is ready for another valid operation. see autoselect command sequence for more information. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see table 10 and table 11 for program com- mand sequence.
56 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information after the program resume command is written, the device reverts to program- ming. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see write op- eration status for more information. the system must write the program resume command (address bits are don?t care) to exit the program suspend mode and continue the programming opera- tion. further writes of the resume command are ignored. another program suspend command can be written after the device has resume programming. figure 3. program suspend/program resume chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is ini- tiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. table 10 and table 11 show the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, or dq2. refer to the write operation status section for information on these status bits. program operation or write-to-buffer sequence in progress write program suspend command sequence command is also valid for erase-suspended-program operations autoselect and secsi sector read operations are also allowed data cannot be read from erase- o r program-suspended sectors write program resume command sequence read data as required done reading? no yes write address/data xxxh/3030h device reverts to operation prior to program suspend write address/data xxxh/b0b0h wait 15 s
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 57 advance information any commands written during the chip er ase operation are ignored, including erase suspend commands. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to en- sure data integrity. figure 4 illustrates the algorithm for the erase operation. note that the secured silicon sector, autoselect, and cfi functions are unavailable when an erase operation in is progress. refer to the erase and program operations table in the ac characteristics section for parameters, and figure 16 section for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two addi- tional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. table 10 and table 11 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the em- bedded erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase address and command following the exceeded time- out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any com- mand other than sector erase or erase suspend during the time-out period resets the device to the read mode. note that the secured silicon sector, autoselect, and cfi functions are unavailable when an erase op- eration in is progress. the system must rewrite the command sequence and any additional addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out (see the section on dq3: sector erase timer.). the time-out begins from the ris- ing edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by reading dq7, dq6, or dq2 in the erasing sector. refer to the write operation status section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset im- mediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. figure 4 illustrates the algorithm for the erase operation. refer to the erase and program operations table in the ac characteristics section for parameters, and figure 16 section for timing diagrams.
58 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information figure 4. erase operation erase suspend/erase resume commands the erase suspend command, b0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, includ- ing the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a typical of 5 s ( maximum of 20 s) to suspend the erase operation. however, when the erase suspend command is written during the sec- tor erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the device enters the erase-sus- pend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) reading at any address within erase-suspended sectors produces sta- tus information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for information on these status bits. after an erase-suspended program operation is complete, the device returns to the erase-suspend-read mode. the system can determine the status of the pro- start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see table 10 and table 11 for program command sequence. 2. see the section on dq3 for information on the sector erase timer.
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 59 advance information gram operation using the dq7 or dq6 status bits, just as in the standard word program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect com- mand sequence. refer to the ?autoselect command sequence? section on page 50 sections for details. to resume the sector erase operation, the system must write the erase resume command. the address of the erase-suspended sector is required when writing this command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. lock register command set definitions the lock register command set permits the user to one-time program the se- cured silicon sector protection bit, persistent protection mode lock bit, and password protection mode lock bit. the lock register bits are all readable after an initial access delay. the lock register command set entry command sequence must be issued prior to any of the following commands listed, to enable proper command execution. note that issuing the lock register command set entry command disables reads and writes for the flash memory . ? lock register program command ? lock register read command the lock register command set exit command must be issued after the ex- ecution of the commands to reset the device to read mode. otherwise the device will hang. if this happens, the flash device must be reset. please refer to reset# for more information. it is important to note that the device will be in either per- sistent protection mode or password pr otection mode depending on the mode selected prior to the device hang. for either the secured silicon sector to be locked, or the device to be perma- nently set to the persistent protection mode or the password protection mode, the associated lock register bits must be programmed. note that the persistent protection mode lock bit and password protection mode lock bit can never be programmed together at the same time. if so, the lock register program operation will abort . the lock register command set exit command must be initiated to re- enable reads and writes to the main memory. password protection command set definitions the password protection command set permits the user to program the 64-bit password, verify the programming of the 64-bit password, and then later unlock the device by issuing the valid 64-bit password. the password protection command set entry command sequence must be issued prior to any of the following commands listed, to enable proper command execution. note that issuing the password protection command set entry command disables reads and writes for the main memory . ? password program command
60 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information the password program command permits programming the password that is used as part of the hardware protection scheme. the actual password is 64-bits long. there is no special addressing order required for programming the pass- word. the password is programmed in 8-bit or 16-bit portions. each portion requires a password program command. once the password is written and verified, the password protection mode lock bit in the ?lock register? must be programmed in order to prevent verification. the password program command is only capable of programming ?0?s. programming a ?1? after a cell is programmed as a ?0? results in a time-out by the embedded program algorithm? with the cell remaining as a ?0?. the password is all f's when shipped from the factory. all 64-bit password combinations are valid as a password. ? password read command the password read command is used to verify the password. the password is verifiable only when the password protection mode lock bit in the ?lock register? is not programmed. if the password protection mode lock bit in the ?lock regis- ter? is programmed and the user attempts to read the password, the device will always drive all f's onto the dq data bus. the lower two address bits (a1-a0) for word mode and (a1-a-1) for by byte mode are valid during the password read, password program, and password unlock commands. writing a ?1? to any other address bits (a max -a2) will abort the password read, password program, and password unlock com- mands and return the device to reading memory array. the address bits (a1-a0) for word mode and (a1-a-1) for byte mode must be entered into the device sequentially for password read and password unlock commands . ? password unlock command the password unlock command is used to clear the ppb lock bit to the ?unfreeze state? so that the ppb bits can be modified. the exact password must be entered in order for the unlocking function to occur. this 64-bit password unlock com- mand sequence will take at least 2 s to process each time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match a password. if another password unlock is issued be- fore the 64-bit password check execution window is completed, the command will be ignored. the password unlock function is accomplished by writing password unlock com- mand and data to the device to perform the clearing of the ppb lock bit to the ?unfreeze state?. the password is 64 bits long. a1 and a0 are used for matching in word mode and a1, a0, a-1 in byte mode. writing the password unlock com- mand does not need to be address order specific. an example sequence is starting with the lower address a1-a0= 00, followed by a1-a0= 01, a1-a0= 10, and a1-a0= 11 if device is configured to operate in word mode. approximately 2 s is required for unlocking the device after the valid 64-bit password is given to the device. it is the responsibility of the mi- croprocessor to keep track of the entering the portions of the 64-bit password with the password unlock command, the order, and when to read the ppb lock bit to confirm successful password unlock . in order to re-lock the device into the password protection mode, the ppb lock bit set com- mand can be re-issued.
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 61 advance information the password protection command set exit command must be issued after the execution of the commands listed previously to reset the device to read mode. otherwise the device will hang. note that issuing the password protection command set exit command re- enables reads and writes for the main memory . non-volatile sector protection command set definitions the non-volatile sector protection command set permits the user to program the persistent protection bits (ppb bits), erase all of the persistent protection bits (ppb bits), and read the logic state of the persistent protection bits (ppb bits). the non-volatile sector protection command set entry command se- quence must be issued prior to any of the commands listed following to enable proper command execution. note that issuing the non-volatile sector protection command set entry command disables reads and writes for the main memory . ? ppb program command the ppb program command is used to program, or set, a given ppb bit. each ppb bit is individually programmed (but is bulk erased with the other ppb bits). the specific sector address (a24-a16 for s29gl512n, a23-a16 for s29gl256n, a22- a16 for s29gl128n) is written at the same time as the program command. if the ppb lock bit is set to the ?freeze state?, the ppb program command will not exe- cute and the command will time-out without programming the ppb bit. ? all ppb erase command the all ppb erase command is used to erase all ppb bits in bulk. there is no means for individually erasing a specific ppb bit. unlike the ppb program, no spe- cific sector address is required. however, when the all ppb erase command is issued, all sector ppb bits are erased in parallel. if the ppb lock bit is set to ?freeze state?, the all ppb erase command will not execute and the command will time-out without erasing the ppb bits. the device will preprogram all ppb bits prior to erasing when issuing the all ppb erase command. also note that the total number of ppb program/erase cycles has the same endurance as the flash memory array. ? ppb status read command the programming state of the ppb for a given sector can be verified by writing a ppb status read command to the device. this requires an initial access time latency. the non-volatile sector protection command set exit command must be issued after the execution of the commands listed previously to reset the device to read mode. note that issuing the non-volatile sector protection command set exit command re-enables reads and writes for the main memory . global volatile sector protection freeze command set the global volatile sector protection freeze command set permits the user to set the ppb lock bit and reading the logic state of the ppb lock bit. the global volatile sector protection freeze command set entry com- mand sequence must be issued prior to any of the commands listed following to enable proper command execution.
62 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information reads and writes from the main memory are allowed. ? ppb lock bit set command the ppb lock bit set command is used to set the ppb lock bit to the ?freeze state? if it is cleared either at reset or if the password unlock command was successfully executed. there is no ppb lock bit clear command. once the ppb lock bit is set to the ?freeze state?, it cannot be cleared unless the device is taken through a power-on clear (for persistent protection mode) or the password unlock command is executed (for password protection mode). if the password protection mode lock bit is programmed, the ppb lock bit status is reflected as set to the ?freeze state?, even after a power-on reset cycle. ? ppb lock bit status read command the programming state of the ppb lock bit can be verified by executing a ppb lock bit status read command to the device. the global volatile sector protection freeze command set exit command must be issued after the execution of the commands listed previously to reset the device to read mode. volatile sector protection command set the volatile sector protection command set permits the user to set the dynamic protection bit (dyb) to the ?protected state?, clear the dynamic protection bit (dyb) to the ?unprotected state?, and read the logic state of the dynamic protec- tion bit (dyb). the volatile sector protection command set entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. note that issuing the volatile sector protection command set entry com- mand disables reads for the bank selected with the command . reads and writes for other banks excluding that bank are allowed . ? dyb set command ? dyb clear command the dyb set and dyb clear commands are used to protect or unprotect a dyb for a given sector. the high order address bits are issued at the same time as the code 00h or 01h on dq7-dq0. all other dq data bus pins are ignored during the data write cycle. the dyb bits are modifiable at any time, regardless of the state of the ppb bit or ppb lock bit. the dyb bits are cleared to the ?unprotected state? at power-up or hardware reset. ?dyb status read command the programming state of the dyb bit for a given sector can be verified by writing a dyb status read command to the device. this requires an initial access delay. the volatile sector protection command set exit command must be issued after the execution of the commands listed previously to reset the device to read mode. note that issuing the volatile sector protection command set exit com- mand re-enables reads and writes to the main memory . secured silicon sector entry command the secured silicon sector entry command allows the following commands to be executed
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 63 advance information ? read from secured silicon sector ? program to secured silicon sector once the secured silicon sector entry command is issued, the secured silicon sector exit command has to be issued to exit secured silicon sector mode. secured silicon sector exit command the secured silicon sector exit command may be issued to exit the secured sil- icon sector mode.
64 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information command definitions ta b l e 1 0 . s29gl512n, s29gl256n, s29gl128n command definitions, x16 command (notes) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (6) 1 ra rd reset (7) 1 xxx f0 autoselect (note 8) manufacturer id 4 555 aa 2aa 55 555 90 x00 01 device id 4 555 aa 2aa 55 555 90 x01 227e x0e note 17 x0f note 17 sector protect verify 4 555 aa 2aa 55 555 90 (sa) x02 xx00 xx01 secure device verify (9) 4 555 aa 2aa 55 555 90 x03 note 10 cfi query (11) 1 555 98 program 4 555 aa 2aa 55 555 a0 pa pd write to buffer 3 555 aa 2aa 55 sa 25 sa wc pa pd wbl pd program buffer to flash (confirm) 1 sa 29 write-to-buffer-abort reset (16) 3 555 aa 2aa 55 555 f0 unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program (12) 2 xxx a0 pa pd unlock bypass sector erase (12) 2 xxx 80 sa 30 unlock bypass chip erase (12) 2 xxx 80 xxx 10 unlock bypass reset (13) 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend/program suspend (14) 1 xxx b0 erase resume/program resume (15) 1 xxx 30 sector command definitions secured silicon sector secured silicon sector entry 3 555 aa 2aa 55 555 88 secured silicon sector exit (18) 4 555 aa 2aa 55 555 90 xx 00 lock register command set definitions lock register lock register command set entry 3 555 aa 2aa 55 555 40 lock register bits program (22) 2 xxx a0 xxx data lock register bits read (22) 1 00 data lock register command set exit (18, 23) 2 xxx 90 xxx 00 password protection command set definitions
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 65 advance information legend: x = don?t care ra = address of the memory to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of the we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a max ?a16 uniquely select any sector. wbl = write buffer location. the address must be within the same write buffer page as pa. password password protection command set entry 3 555 aa 2aa 55 555 60 password program (20) 2 xxx a0 pwa x pwd x password read (19) 4 xxx pwd 0 01 pwd 1 02 pwd 2 03 pwd 3 password unlock (19) 7 00 25 00 03 00 pwd 0 01 pwd 1 02 pwd 2 03 pwd 3 00 29 password protection command set exit (18, 23) 2 xxx 90 xxx 00 non-volatile sector protection command set definitions ppb nonvolatile sector protection command set entry 3 555 aa 2aa 55 555 c0 ppb program (24, 25) 2 xxx a0 sa 00 all ppb erase 2 xxx 80 00 30 ppb status read (25) 1 sa rd (0) non-volatile sector protection command set exit (18) 2 xxx 90 xxx 00 global non-volatile sector protection freeze command set definitions ppb lock bit global non-volatile sector protection freeze command set entry 3 555 aa 2aa 55 555 50 ppb lock bit set (25) 2 xxx a0 xxx 00 ppb lock status read (25) 1 xxx rd (0) global non-volatile sector protection freeze command set exit (18) 2 xxx 90 xxx 00 volatile sector protection command set definitions dyb volatile sector protection command set entry 3 555 aa 2aa 55 555 e0 dyb set (24, 25) 2 xxx a0 sa 00 dyb clear (25) 2 xxx a0 sa 01 dyb status read (25) 1 sa rd (0) volatile sector protection command set exit (18) 2 xxx 90 xxx 00 command (notes) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data
66 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information wc = word count is the number of write buffer locations to load minus 1. pwd = password pwd x = password word0, word1, word2, and word3. data = lock register contents: pd(0) = secured silicon sector prot ection bit, pd(1) = persistent protection mode lock bit, pd(2 ) = password protection mode lock bit. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle, and the 4th, 5th, and 6th cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15-dq8 are don't cares for unlock and command cycles. 5. address bits a max :a16 are don't cares for unlock and command cycles, unless sa or pa required. (a max is the highest address pin.). 6. no unlock or command cycles required when reading array data. 7. the reset command is required to return to reading array data when device is in the autoselect mode, or if dq5 goes high (while the device is providing status data). 8. the fourth, fifth, and sixth cycle of the autoselect command sequence is a read cycle. 9. the data is 00h for an unprotected sector and 01h for a protected sector. see ?autoselect command sequence? for more information. this is same as ppb status read except that the protect and unprotect statuses are inverted here. 10. the data value for dq7 is ?1? for a serialized and protected otp region and ?0? for an unserialized and unprotected secured silicon sector region. see ?secured silicon sector flash memo ry region? for more information. for am29lvxxxmh: xx18h/ 18h = not factory locked. xx98h/98h = factory locked. fo r am29lvxxxml: xx08h/08h = not factory locked. xx88h/88h = factory locked. 11. command is valid when device is ready to read array data or when device is in autoselect mode. 12. the unlock-bypass command is required prior to the unlock-bypass-program command. 13. the unlock-bypass-reset command is required to return to reading array data when the device is in the unlock bypass mode. 14. the system may read and program/program suspend in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 15. the erase resume/program resume command is valid only during the erase suspend/program suspend modes. 16. issue this command sequence to return to read mode after detecting device is in a write-to-buffer-abort state. note: the full command sequence is required if resetting out of abort while using unlock bypass mode. 17. s29gl512nh/l = 2223h/23h, 220h/01h; s29gl256nh/l = 2222h/22h, 2201h/01h; s29gl128nh/l = 2221h/21h, 2201h/ 01h. 18. the exit command returns the device to reading the array. 19. note that the password portion can be entered or read in any order as long as the entire 64-bit password is entered or read. 20. for pwdx, only one portion of the password can be programmed per each ?a0? command. 21. the all ppb erase command embeds progra mming of all ppb bits before erasure. 22. all lock register bits are one-time programmable. note that the program state = ?0? and the erase state = ?1?. also note that of both the persistent protection mode lock bit and the password protection mode lock bit cannot be programmed at the same time or the lock register bits program operation will abort and return the device to read mode. lock register bits that are reserved for future use will default to ?1's?. the lock register is shipped out as ?ffff's? before lock register bit progra m execution. 23. if any of the entry command was initiated, an exit command must be issued to reset the device into read mode. otherwise the device will hang. 24. if acc = v hh , sector protection will match when acc = v ih 25. protected state = ?00h?, unprotected state = ?01h?.
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 67 advance information ta b l e 1 1 . s29gl512n, s29gl256n, s29gl1 28n command definitions, x8 command (notes) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (6) 1 ra rd reset (7) 1 xxx f0 autoselect manufacturer id 4 aaa aa 555 55 aaa 90 x00 01 device id 4 aaa aa 555 55 aaa 9 x02 xx7e x1c note 17 x1e note 17 sector protect verify 4 aaa aa 555 55 aaa 90 (sa) x04 00 01 secure device verify (9) 4 aaa aa 555 55 aaa 90 x06 note 10 cfi query (11) 1 aaa 98 write to buffer 3 aaa aa 555 55 sa 25 sa wc pa pd wbl pd program buffer to flash (confirm) 1 sa 29 write-to-buffer-abort reset (16) 3 aaa aa pa 55 555 f0 unlock bypass reset (13) 2 xxx 90 xxx 00 chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 sector erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 erase suspend/program suspend (14) 1 xxx b0 erase resume/program resume (15) 1 xxx 30 secured silicon sector command definitions secured silicon sector secured silicon sector entry 3 aaa aa 555 55 aaa 88 secured silicon sector exit (18) 4 aaa aa 555 55 aaa 90 xx 00 lock register command set definitions lock register lock register command set entry 3 aaa aa 555 55 aaa 40 lock register bits program (22) 2 xxx a0 xxx data lock register bits read (22) 1 00 data lock register command set exit (18, 23) 2 xxx 90 xxx 00 password protection command set definitions
68 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information legend: x = don?t care ra = address of the memory to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of the we# or ce# pulse, whichever happens first. password password protection command set entry 3 aaa aa 555 55 aaa 60 password program (20) 2 xxx a0 pwa x pwd x password read (19) 8 00 pwd 0 01 pwd 1 02 pwd 2 03 pwd 3 04 pwd 4 05 pwd 5 06 pwd 6 07 pwd 7 password unlock (19) 11 00 25 00 03 00 pwd 0 01 pwd 1 02 pwd 2 03 pwd 3 04 pwd 4 05 pwd 5 06 pwd 6 07 pwd 7 00 29 password protection command set exit (18, 23) 2 xxx 90 xxx 00 non-volatile sector protection command set definitions ppb nonvolatile sector protection command set entry 3 aaa aa 55 55 aaa c0 ppb program (24, 25) 2 xxx a0 sa 00 all ppb erase 2 xxx 80 00 30 ppb status read (25) 1 sa rd (0) non-volatile sector protection command set exit (18) 2 xxx 90 xxx 00 global non-volatile sector protection freeze command set definitions ppb lock bit global non-volatile sector protection freeze command set entry 3 aaa aa 555 55 aaa 50 ppb lock bit set (25) 2 xxx a0 xxx 00 ppb lock status read (25) 1 xxx rd (0) global non-volatile sector protection freeze command set exit (18) 2 xxx 90 xxx 00 volatile sector protection command set definitions dyb volatile sector protection command set entry 3 aaa aa 555 55 aaa e0 dyb set (24, 25) 2 xxx a0 sa 00 dyb clear (25) 2 xxx a0 sa 01 dyb status read (25) 1 sa rd (0) volatile sector protection command set exit (18) 2 xxx 90 xxx 00 command (notes) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 69 advance information sa = address of the sector to be verified (in autoselect mode) or erased. address bits a max ?a16 uniquely select any sector. wbl = write buffer location. the address must be within the same write buffer page as pa. wc = word count is the number of write buffer locations to load minus 1. pwd = password pwd x = password word0, word1, word2, word3. word 4, word 5, word 6, and word 7. data = lock register contents: pd(0) = secured silicon sector prot ection bit, pd(1) = persistent protection mode lock bit, pd(2 ) = password protection mode lock bit. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle, and the 4th, 5th, and 6th cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15-dq8 are don't cares for unlock and command cycles. 5. address bits a max :a16 are don't cares for unlock and command cycles, unless sa or pa required. (a max is the highest address pin.). 6. no unlock or command cycles required when reading array data. 7. the reset command is required to return to reading array data when device is in the autoselect mode, or if dq5 goes high (while the device is providing status data). 8. the fourth, fifth, and sixth cycle of the autoselect command sequence is a read cycle. 9. the data is 00h for an unprotected sector and 01h for a protected sector. see ?autoselect command sequence? for more information. this is same as ppb status read except that the protect and unprotect statuses are inverted here. 10. the data value for dq7 is ?1? for a serialized and protected otp region and ?0? for an unserialized and unprotected secured silicon sector region. see ?secured silicon sector flash memo ry region? for more information. for am29lvxxxmh: xx18h/ 18h = not factory locked. xx98h/98h = factory locked. fo r am29lvxxxml: xx08h/08h = not factory locked. xx88h/88h = factory locked. 11. command is valid when device is ready to read array data or when device is in autoselect mode. 12. the unlock-bypass command is required prior to the unlock-bypass-program command. 13. the unlock-bypass-reset command is required to return to reading array data when the device is in the unlock bypass mode. 14. the system may read and program/program suspend in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 15. the erase resume/program resume command is valid only during the erase suspend/program suspend modes. 16. issue this command sequence to return to read mode after detecting device is in a write-to-buffer-abort state. note: the full command sequence is required if resetting out of abort while using unlock bypass mode. 17. s29gl512nh/l = 2223h/23h, 220h/01h; s29gl256nh/l = 2222h/22h, 2201h/01h; s29gl128nh/l = 2221h/21h, 2201h/ 01h. 18. the exit command returns the device to reading the array. 19. note that the password portion can be entered or read in any order as long as the entire 64-bit password is entered or read. 20. for pwdx, only one portion of the password can be programmed per each ?a0? command. 21. the all ppb erase command embeds progra mming of all ppb bits before erasure. 22. all lock register bits are one-time programmable. note that the program state = ?0? and the erase state = ?1?. also note that of both the persistent protection mode lock bit and the password protection mode lock bit cannot be programmed at the same time or the lock register bits program operation will abort and return the device to read mode. lock register bits that are reserved for future use will default to ?1's?. the lock register is shipped out as ?ffff's? before lock register bit progra m execution. 23. if any of the entry command was initiated, an exit command must be issued to reset the device into read mode. otherwise the device will hang. 24. if acc = v hh , sector protection will match when acc = v ih protected state = ?00h?, unprotected state = ?01h?. write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 19 and the following subsec- tions describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress.
70 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information the device also provides a hardware-bas ed output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been completed. note that all write operation status dq bits are valid only after 4 s delay. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device outputs on dq7 the com- plement of the datum programmed to dq 7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a pro- gram address falls within a protected sector, data# polling on dq7 is active for approximately 1 s, then the device returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the device returns to the read mode. if not all selected sectors are protected, the em- bedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if the system reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is as- serted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq0?dq6 may be still invalid. valid data on dq0?dq7 will appear on successive read cycles. ta b l e 12 shows the outputs for data# polling on dq7. figure 5 shows the data# polling algorithm. figure 17 in the ac characteristics section shows the data# polling timing diagram.
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 71 advance information figure 5. data# polling algorithm ry /b y# : r ea d y/b u sy# the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. table 12 shows the outputs for ry/by#. dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5.
72 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cy- cles to any address cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algo- rithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is ac- tively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device en- ters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alter- natively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approxi- mately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. ta b l e 12 shows the outputs for toggle bit i on dq6. figure 6 shows the toggle bit algorithm. figure 18 in the ?ac characteristics? section shows the toggle bit tim-
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 73 advance information ing diagrams. figure 19 shows the differences between dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii. figure 6. toggle bit algorithm dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. start no yes yes dq5 = 1? no yes dq6 = toggle? no read byte (dq0-dq7) address = va dq6 = toggle? read byte twice (dq 0-dq7) adrdess = va read byte (dq0-dq7) address = va fail pass note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information.
74 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 12 to compare outputs for dq2 and dq6. figure 6 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? explains the algorithm. see also the ry/by#: ready/busy# subsec- tion. figure 18 shows the toggle bit timing diagram. figure 19 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 6 for the following discussion. whenever the system initially be- gins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has suc- cessfully completed the program or erase operation. if it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as de- scribed in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algo- rithm when it returns to determine the status of the operation (top of figure 6). dq5: exceeded timing limits dq5 indicates whether the program, erase, or write-to-buffer time has ex- ceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the opera- tion, and when the timing limit has been exceeded, dq5 produces a ?1.? in all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode).
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 75 advance information dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to de- termine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between additional sector erase commands from the system can be as- sumed to be less than 50 s, the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept addi- tional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each sub- sequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. ta b l e 12 shows the status of dq3 relative to the other status bits. dq1: write-to-buffer abort dq1 indicates whether a write-to-buffer operation was aborted. under these conditions dq1 produces a ?1?. the system must issue the write-to-buffer-abort- reset command sequence to return the device to reading array data. see write buffer section for more details.
76 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information ta b l e 1 2 . write operation status notes: 1. dq5 switches to ?1? when an embedded program, embedded erase, or write-to-buffer operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. the data# polling algorithm should be used to monitor the last loaded write-buffer address location. 4. dq1 switches to ?1? when the device has aborted the write-to-buffer operation absolute maximum ratings storage temperature, plastic packages . . . . . . . . . . . . . . . . ?65c to +150c ambient temperature with power applied . . . . . . . . . . . . . . ?65c to +125c voltage with respect to ground: v cc (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v v io . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .?0.5 v to +4.0 v a9, oe#, acc and reset# (note 2) . . . . . . . . . . . . . ?0.5 v to +12.5 v all other pins (note 1) . . . . . . . . . . . . . . . . . . . . ?0.5 v to v cc +12.5 v output short circuit current (note 3) . . . . . . . . . . . . . . . . . . . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/os is ?0.5 v. during voltage transitions, inputs or i/os may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 7 . maximum dc voltage on input or i/os is v cc + 0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 8 . 2. minimum dc input voltage on pins a9, oe#, acc, and reset# is ?0.5 v. during voltage transitions, a9, oe#, acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 7 . maximum dc input voltage on pin a9, oe#, acc, and reset# is +12.5 v which may overshoot to +14.0v for periods up to 20 ns. 3 . n o m or e th a n on e ou t p u t ma y b e s h or t e d t o g r ou n d a t a ti me . d u r a t io n of t h e sh o r t circuit should not be greater than one second. 4. stresses above those listed under ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 ry/ by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 0 embedded erase algorithm 0 toggle 0 1 toggle n/a 0 program suspend mode program- suspend read program-suspended sector invalid (not allowed) 1 non-program suspended sector data 1 erase suspend mode erase- suspend read erase-suspended sector 1 no toggle 0 n/a toggle n/a 1 non-erase suspended sector data 1 erase-suspend-program (embedded program) dq7# toggle 0 n/a n/a n/a 0 write-to- buffer busy (note 3) dq7# toggle 0 n/a n/a 0 0 abort (note 4) dq7# toggle 0 n/a n/a 1 0
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 77 advance information of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions fo r extended periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c supply voltages v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 v to +3.6 v v io (note 2) . . . . . . . . . . . . . . . . . . . . +1.65 v to +1.95 v or +2.7 to 3.6 v notes: 1. operating ranges define those limits between which the functionality of the device is guaranteed. 2. the i/os will not operate at 3 v when v io =1.8 v. figure 7. maximum negative overshoot waveform figure 8. maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
78 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information dc characteristics cmos compatible notes: 1. the i cc current listed is typically less than tbd ma/mhz, with oe# at v ih . 2. i cc active while embedded erase or embedded program or write buffer programming is in progress. 3. not 100% tested. 4. automatic sleep mode enables the lower power mode when addresses remain stable tor t acc + 30 ns. 5. v io = 1.65?3.6 v 6. v cc = 3 v and v io = 3v or 1.8v. when v io is at 1.8v, i/o pins cannot operate at 3v. parameter symbol parameter description (notes) test conditions min typ max unit i li input load current (1) v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9 input load current v cc = v cc max ; a9 = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i io1 v io active read current (switching current) v io = 1.8 v, ce# = v il , oe# = v il , we# = v il , f = 5 mhz 510a i io2 v io non-active output ce# = v il, oe# = v ih 0.2 10 ma i cc1 v cc active read current (1) ce# = v il, oe# = v ih , v cc = v ccmax , f = 5 mhz, byte mode 25 30 ma ce# = v il, oe# = v ih , v cc = v ccmax , f = 5 mhz, word mode 25 30 i cc2 v cc initial page read current (1) ce# = v il, oe# = v ih, v cc = v ccmax 50 60 ma i cc3 v cc intra-page read curren t (1) ce# = v il, oe# = v ih, v cc = v ccmax 10 20 ma i cc4 v cc active erase/program current (2, 3) ce# = v il, oe# = v ih, v cc = v ccmax 50 60 ma i cc5 v cc standby current ce#, reset# = v ss 0.3 v, oe# = v ih, v cc = v ccmax 15a i cc6 v cc reset current v cc = v ccmax; reset# = v ss 0.3 v 15a i cc7 automatic sleep mode (4) v cc = v ccmax v ih = v cc 0.3 v, v il = v ss 0.3 v, wp#/acc = v ih 15a i acc acc accelerated program current ce# = v il, oe# = v ih, v cc = v ccmax, wp#/acc = v ih wp#/acc pin 10 20 ma v cc pin 30 60 v il input low voltage (5) ?0.5 0.3 x v io v v ih input high voltage (5) 0.7 x v io v io + 0.3 v v hh voltage for acc erase/program acceleration v cc = 2.7 ?3.6 v 11.5 12.5 v v id voltage for autoselect and temporary sector unprotect v cc = 2.7 ?3.6 v 11.5 12.5 v v ol output low voltage (5) i ol = 100 a 0.15 x v io v v oh output high voltage (5) i oh = 100 a 0.85 x v io v v lko low v cc lock-out voltage (3) 2.3 2.5 v
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 79 advance information test conditions note: if v io < v cc , the reference level is 0.5 v io . key to switching waveforms note: diodes are in3064 or equivalent table 13. test specifications 2.7 k c l 6.2 k 3.3 v device under test note: diodes are in3064 or equivalent. figure 9. test setup test condition all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?v io v input timing measurement reference levels (see note) 0.5v io v output timing measurement reference levels 0.5 v io v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) v io 0.0 v 0.5 v io 0.5 v io v output measurement level input note: if v io < v cc , the input measurement reference level is 0.5 v io . figure 10. input waveforms and measurement levels
80 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information ac characteristics read-only operations?s29gl512n only notes: 1. not 100% tested. 2. ce#, oe# = v il 3. oe# = v il 4. see figure 9 and table 13 for test specifications. 5. unless otherwise indicated, ac specifications for 90 ns and 100 ns speed options are tested with v io = v cc = 3 v. ac specifications for 100 ns and 110 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. parameter description test setup speed options jedec std. 90 100 100 110 unit t avav t rc read cycle time v io = v cc = 3 v min 90 100 ns v io = 2.5 v, v cc = 3 v (note 1) 100 110 v io = 1.8 v, v cc = 3 v 100 110 ns t avqv t acc address to output delay (note 2) v io = v cc = 3 v max 90 100 ns v io = 2.5 v, v cc = 3 v (note 1) 100 110 v io = 1.8 v, v cc = 3 v 100 110 ns t elqv t ce chip enable to output delay (note 3) v io = v cc = 3 v max 90 105 ns v io = 2.5 v, v cc = 3 v (note 1) 100 110 v io = 1.8 v, v cc = 3 v 100 110 ns t pac c page access time max 25 25 35 35 ns t glqv t oe output enable to output delay max 25 25 35 35 ns t ehqz t df chip enable to output high z (note 1) max 20 ns t ghqz t df output enable to output high z (note 1) max 20 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 81 advance information ac characteristics read-only operations?s29gl256n only notes: 1. not 100% tested. 2. ce#, oe# = v il 3. oe# = v il 4. see figure 9 and table 13 for test specifications. 5. unless otherwise indicated, ac specifications for 80 ns and 90 ns speed options are tested with v io = v cc = 3 v. ac specifications for 90 ns and 100 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. parameter description test setup speed options jedec std. 80 90 90 100 unit t avav t rc read cycle time v io = v cc = 3 v min 80 90 ns v io = 2.5 v, v cc = 3 v (note 1) 90 100 v io = 1.8 v, v cc = 3 v 90 100 ns t avqv t acc address to output delay (note 2) v io = v cc = 3 v max 80 90 ns v io = 2.5 v, v cc = 3 v (note 1) 90 100 v io = 1.8 v, v cc = 3 v 90 100 ns t elqv t ce chip enable to output delay (note 3) v io = v cc = 3 v max 80 90 ns v io = 2.5 v, v cc = 3 v (note 1) 90 100 v io = 1.8 v, v cc = 3 v 90 100 ns t pac c page access time max 25 25 35 35 ns t glqv t oe output enable to output delay max 25 25 35 35 ns t ehqz t df chip enable to output high z (note 1) max 20 ns t ghqz t df output enable to output high z (note 1) max 20 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns
82 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information ac characteristics read-only operations?s29gl128n only notes: 1. not 100% tested. 2. ce#, oe# = v il 3. oe# = v il 4. see figure 9 and table 13 for test specifications. 5. unless otherwise indicated, ac specifications for 80 ns and 90 ns speed options are tested with v io = v cc = 3 v. ac specifications for 90 ns and 100 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. parameter description test setup speed options jedec std. 80 90 90 100 unit t avav t rc read cycle time v io = v cc = 3 v min 80 90 ns v io = 2.5 v, v cc = 3 v (note 1) 90 100 v io = 1.8 v, v cc = 3 v 90 100 ns t avqv t acc address to output delay (note 2) v io = v cc = 3 v max 80 90 ns v io = 2.5 v, v cc = 3 v (note 1) 90 100 v io = 1.8 v, v cc = 3 v 90 100 ns t elqv t ce chip enable to output delay (note 3) v io = v cc = 3 v max 80 90 ns v io = 2.5 v, v cc = 3 v (note 1) 90 100 v io = 1.8 v, v cc = 3 v 90 100 ns t pac c page access time max 25 25 35 35 ns t glqv t oe output enable to output delay max 25 25 35 35 ns t ehqz t df chip enable to output high z (note 1) max 20 ns t ghqz t df output enable to output high z (note 1) max 20 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 83 advance information ac characteristics note: figure shows word mode. addresses are a2?a-1 for byte mode. figure 12. page read timings figure 11. read operation timings t oh t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df a23 - a2 ce# oe# a1 - a0* data bus same page aa ab ac ad qa qb qc qd t acc t pac c t pac c t pac c
84 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information ac characteristics hardware reset (reset#) note: not 100% tested. if ramp rate is equal to or faster than 1v/100s with a falling edge of the reset# pin initiated, the reset# pin needs to be held low only for 100s for power-up. parameter description all speed options unit jedec std. t ready reset# pin low (during embedded algorithms) to read mode (see note) max 1 ms t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 1 ms t rp reset# pulse width min 1 ms t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb figure 13. reset timings
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 85 advance information ac characteristics erase and program operations ?s29gl512n only notes: 1. not 100% tested. 2. see the ?ac characteristics? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specific ation is based upon a 16-word/32-byte write buffer operation. 5. unless otherwise indicated, ac specifications for 90 ns and 100 ns speed options are tested with v io = v cc = 3 v. ac specifications for 100 ns and 110 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. parameter speed options jedec std. description 90 100 100 110 unit t avav t wc write cycle time (note 1) min 90 100 100 110 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 45 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ tbd s effective write buffer program operation (notes 2, 4) per word typ tbd s accelerated effective write buffer program operation (notes 2, 4) per word typ tbd s program operation (note 2) word typ tbd s accelerated programming operation (note 2) word typ tbd s t whwh2 t whwh2 sector erase operation (note 2) typ tbd sec t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 50 s
86 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information ac characteristics erase and program operations ?s29gl256n only notes: 1. not 100% tested. 2. see the ?ac characteristics? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specific ation is based upon a 16-word/32-byte write buffer operation. 5. unless otherwise indicated, ac specifications for 80 ns and 90 ns speed options are tested with v io = v cc = 3 v. ac specifications for 90 ns and 100 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. parameter speed options jedec std. description 80 90 90 100 unit t avav t wc write cycle time (note 1) min 80 90 90 100 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 45 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ tbd s effective write buffer program operation (notes 2, 4) per word typ tbd s accelerated effective write buffer program operation (notes 2, 4) per word typ tbd s program operation (note 2) word typ tbd s accelerated programming operation (note 2) word typ tbd s t whwh2 t whwh2 sector erase operation (note 2) typ tbd sec t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 50 s
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 87 advance information ac characteristics erase and program operations ?s29gl128n only notes: 1. not 100% tested. 2. see the ?ac characteristics? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specific ation is based upon a 16-word/32-byte write buffer operation. 5. unless otherwise indicated, ac specifications for 80 ns and 90 ns speed options are tested with v io = v cc = 3 v. ac specifications for 90 ns and 100 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. parameter speed options jedec std. description 80 90 90 100 unit t avav t wc write cycle time (note 1) min 80 90 90 100 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 45 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ tbd s effective write buffer program operation (notes 2, 4) per word typ tbd s accelerated effective write buffer program operation (notes 2, 4) per word typ tbd s program operation (note 2) word typ tbd s accelerated programming operation (note 2) word typ tbd s t whwh2 t whwh2 sector erase operation (note 2) typ tbd sec t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 50 s
88 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information ac characteristics notes: 1. not 100% tested. 2. ce#, oe# = v il 3. oe# = v il 4. see figure 9 and table 13 for test specifications. oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa n otes: 1 . pa = program address, pd = program data, d out is the true data at the program address. 2 . illustration shows device in word mode. figure 14. program operation timings acc t vhh v hh v il or v ih v il or v ih t vhh figure 15. accelerated program timing diagram
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 89 advance information ac characteristics oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 3030h t ds t vcs t cs t dh 5555h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy notes: 1. sa = sector address (for sector erase), va = valid address for reading status data (see ?write operation status?. 2. these waveforms are for the word mode. figure 16. chip/sector erase operation timings
90 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information ac characteristics we# ce# oe# high z t oe high z dq15 and dq7 dq14?dq8, dq6?dq0 ry/by# t busy complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc note: va = valid address. illustration shows first status cy cle after command sequence, last status read cycle, and array data read cycle . figure 17. data# polling timings (during embedded algorithms)
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 91 advance information ac characteristics oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6 & dq14/ dq2 & dq10 valid data valid status valid status valid status ry/by# note: va = valid address; not required for dq6. illust ration shows first two status cycle after command sequence, last status read cycle, and array data read cycle figure 18. toggle bit timings (during embedded algorithms) note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6 . figure 19. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
92 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information ac characteristics alternate ce# controlled erase and program operations ?s29gl512n only notes: 1. not 100% tested. 2. see the ?ac characteristics? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specific ation is based upon a 16-word/32-byte write buffer operation. 5. unless otherwise indicated, ac specifications for 90 ns and 100 ns speed options are tested with v io = v cc = 3 v. ac specifications for 100 ns and 110 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. parameter speed options jedec std. description 90 100 100 110 unit t avav t wc write cycle time (note 1) min 90 100 100 110 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 45 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 45 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ tbd s effective write buffer program operation (notes 2, 4) per word typ tbd s effective accelerated write buffer program operation (notes 2, 4) per word typ tbd s program operation (note 2) word typ tbd s accelerated programming operation (note 2) word typ tbd s t whwh2 t whwh2 sector erase operation (note 2) typ tbd sec
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 93 advance information ac characteristics alternate ce# controlled erase and program operations ?s29gl256n only notes: 1. not 100% tested. 2. see the ?ac characteristics? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specific ation is based upon a 16-word/32-byte write buffer operation. 5. unless otherwise indicated, ac specifications for 80 ns and 90 ns speed options are tested with v io = v cc = 3 v. ac specifications for 90 ns and 100 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. parameter speed options jedec std. description 80 90 90 100 unit t avav t wc write cycle time (note 1) min 80 90 90 100 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 45 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 45 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ tbd s effective write buffer program operation (notes 2, 4) per word typ tbd s effective accelerated write buffer program operation (notes 2, 4) per word typ tbd s program operation (note 2) word typ tbd s accelerated programming operation (note 2) word typ tbd s t whwh2 t whwh2 sector erase operation (note 2) typ tbd sec
94 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information ac characteristics alternate ce# controlled erase and program operations ?s29gl128n only notes: 1. not 100% tested. 2. see the ?ac characteristics? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specific ation is based upon a 16-word/32-byte write buffer operation. 5. unless otherwise indicated, ac specifications for 80 ns and 90 ns speed options are tested with v io = v cc = 3 v. ac specifications for 90 ns and 100 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. parameter speed options jedec std. description 80 90 90 100 unit t avav t wc write cycle time (note 1) min 80 90 90 100 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 45 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 45 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ tbd s effective write buffer program operation (notes 2, 4) per word typ tbd s effective accelerated write buffer program operation (notes 2, 4) per word typ tbd s program operation (note 2) word typ tbd s accelerated programming operation (note 2) word typ tbd s t whwh2 t whwh2 sector erase operation (note 2) typ tbd sec
june 14, 2004 s29glxxxn_00_a4 s29glxxxn mirrorbit tm flash family 95 advance information ac characteristics latchup characteristics note: includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. description min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe#, and reset#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. waveforms are for the word mode. figure 20. alternate ce# controlled write (erase/program) operation timings
96 s29glxxxn mirrorbit tm flash family s29glxxxn_00_a4 june 14, 2004 advance information erase and programming performance notes: 1. typical program and erase times assume the following conditions: 10,000 cycles, 25c, 3.0 v v cc , checkerboard pattern. 2. under worst case conditions of 100,000 cycles, 90c, v cc = 3.0 v. 3. effective write buffer specification is ba sed upon a 16-word write buffer operation. 4. the typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum program times listed. 5. in the pre-programming step of the embedded erase algorithm, all bits are programmed to 00h before erasure. 6. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 17 for further information on command definitions. tsop pin and bga package capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter typ (note 1) max (note 2) unit comments sector erase time tbd tbd sec excludes 00h programming prior to erasure (note 5) chip erase time s29gl128n tbd tbd sec s29gl256n tbd tbd s29gl512n tbd tbd total write buffer time (note 3) tbd tbd s excludes system level overhead (note 6) total accelerated effective write buffer programming time (note 3) tbd tbd s chip program time s29gl128n tbd tbd sec s29gl256n tbd tbd s29gl512n tbd tbd parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 tsop 6 7.5 pf c out output capacitance v out = 0 tsop 8.5 12 pf c in2 control pin capacitance v in = 0 tsop 7.5 9 pf
august 30, 2004 psram_type01_12_a1 psram type 1 97 advance information psram type 1 4mbit (256k word x 16-bit) 8mbit (512k word x 16-bit) 16mbit (1m word x 16-bit) 32mbit (2m word x 16-bit) 64mbit (4m word x 16-bit) functional description absolute maximum ratings mode ce# ce2/zz# oe# we# ub# lb# addresses i/o 1-8 i/o 9-16 power read (word) l h l h l l x dout dout i active read (lower byte) l h l h h l x dout high-z i active read (upper byte) l h l h l h x high-z dout i active write (word) l h x l l l x din din i active write (lower byte) l h x l h l x din invalid i active write (upper byte) l h x l l h x invalid din i active outputs disabled l h h h x x x high-z high-z i active standby h h x x x x x high-z high-z i standby deep power down h l x x x x x high-z high-z i deep sleep item symbol ratings units voltage on any pin relative to v ss vin, vout -0.2 to v cc +0.3 v voltage on v cc relative to v ss v cc -0.2 to 3.6 v power dissipation p d 1 w storage temperature t stg -55 to 150 c operating temperature t a -25 to 85 c
98 psram type 1 psram_type01_12_a1 august 30, 2004 advance information dc characteristics (4mb psram asynchronous) asynchronous performance grade -70 density 4mb psram symbol parameter conditions min max units v cc power supply 2.7 3.3 v v ih input high level 0.8 vccq v cc + 0.3 v v il input low level -0.3 0.4 v i il input leakage current vin = 0 to v cc 0.5 a i lo output leakage current oe = v ih or chip disabled 0.5 a v oh output high voltage i oh = -1.0 ma v i oh = -0.2 ma 0.8 vccq i oh = -0.5 ma v ol output low voltage i ol = 2.0 ma v i ol = 0.2 ma 0.2 i ol = 0.5 ma i active operating current v cc = 3.3 v 25 ma i standby standby current v cc = 3.0 v 70 a v cc = 3.3 v i deep sleep deep power down current xa i par 1/4 1/4 array par current xa i par 1/2 1/2 array par current xa
august 30, 2004 psram_type01_12_a1 psram type 1 99 advance information dc characteristics (8mb psram asynchronous) asynchronous version b c performance grade -55 -70 -70 density 8mb psram 8mb psram 8mb psram symbol parameter conditions min max units min max units min max units v cc power supply 2.7 3.3 v 2.7 3.6 v 2.7 3.3 v v ih input high level 2.2 v cc + 0.3 v 2.2 v cc + 0.3 v 0.8 v cc +0.3 v v il input low level -0.3 0.6 v -0.3 0.6 v -0.3 0.4 v i il input leakage current vin = 0 to v cc 0.5 a 0.5 a 0.5 a i lo output leakage current oe = v ih or chip disabled 0.5 a 0.5 a 0.5 a v oh output high voltage i oh = -1.0 ma v cc -0.4 v v cc -0.4 vv i oh = -0.2 ma 0.8 v ccq i oh = -0.5 ma v ol output low voltage i ol = 2.0 ma 0.4 v 0.4 vv i ol = 0.2 ma 0.2 i ol = 0.5 ma i active operating current v cc = 3.3 v 25 ma 23 ma 25 ma i standby standby current v cc = 3.0 v 60 a 60 a 70 a v cc = 3.3 v i deep sleep deep power down current xa xa xa i par 1/4 1/4 array par current xa xa xa i par 1/2 1/2 array par current xa xa xa
100 psram type 1 psram_type01_12_a1 august 30, 2004 advance information dc characteristics (16mb psram asynchronous) asynchronous performance grade -55 -70 density 16mb psram 16mb psram symbol parameter conditions minimum maximum units minimum maximum units v cc power supply 2.7 3.6 v 2.7 3.6 v v ih input high level 2.2 v cc + 0.3 v 2.2 v cc + 0.3 v v il input low level -0.3 0.6 v -0.3 0.6 v i il input leakage current vin = 0 to v cc 0.5 a 0.5 a i lo output leakage current oe = v ih or chip disabled 0.5 a 0.5 a v oh output high voltage i oh = -1.0 ma v cc -0.4 v v cc -0.4 v i oh = -0.2 ma i oh = -0.5 ma v ol output low voltage i ol = 2.0 ma 0.4 v 0.4 v i ol = 0.2 ma i ol = 0.5 ma i active operating current v cc = 3.3 v 25 ma 25 ma i standby standby current v cc = 3.0 v 100 a 100 a v cc = 3.3 v i deep sleep deep power down current x a x a i par 1/4 1/4 array par current x a x a i par 1/2 1/2 array par current x a x a
august 30, 2004 psram_type01_12_a1 psram type 1 101 advance information dc characteristics (1 6mb psram page mode) page mode performance grade -60 -65 -70 density 16mb psram 16mb psram 16mb psram symbol parameter conditions min max units min max units min max units v cc power supply 2.7 3.3 v 2.7 3.3 v 2.7 3.3 v v ih input high level 0.8 vccq v cc + 0.2 v 0.8 vccq v cc + 0.2 v 0.8 vccq v cc + 0.2 v v il input low level -0.2 0.2 vccq v -0.2 0.2 vccq v -0.2 0.2 vccq v i il input leakage current vin = 0 to v cc 1a 1a 1a i lo output leakage current oe = v ih or chip disabled 1a 1a 1a v oh output high voltage i oh = -1.0 ma vv v i oh = -0.2 ma i oh = -0.5 ma 0.8 vccq 0.8 vccq 0.8 vccq v ol output low voltage i ol = 2.0 ma vv v i ol = 0.2 ma i ol = 0.5 ma 0.2 vccq 0.2 vccq 0.2 vccq i active operating current v cc = 3.3 v 25 ma 25 ma 25 ma i standby standby current v cc = 3.0 v a a a v cc = 3.3 v 100 100 100 i deep sleep deep power down current 10 a 10 a 10 a i par 1/4 1/4 array par current 65 a 65 a 65 a i par 1/2 1/2 array par current 80 a 80 a 80 a
102 psram type 1 psram_type01_12_a1 august 30, 2004 advance information dc characteristics (32mb psram page mode) page mode version c e performance grade -65 -60 -65 -70 density 32mb psram 32mb psram 32mb psram 32mb psram symbol parameter conditions min max units min max units min max units min max units v cc power supply 2.7 3.6 v 2.7 3.3 v 2.7 3.3 v 2.7 3.3 v v ih input high level 1.4 v cc + 0.2 v0.8 vccq v cc + 0.2 v 0.8 vccq v cc + 0.2 v 0.8 vccq v cc + 0.2 v v il input low level -0.2 0.4 v -0.2 0.2 vccq v-0.2 0.2 vccq v-0.2 0.2 vccq v i il input leakage current vin = 0 to v cc 0.5 a 1 a 1 a 1 a i lo output leakage current oe = v ih or chip disabled 0.5 a 1 a 1 a 1 a v oh output high voltage i oh = -1.0 ma vv vv i oh = -0.2 ma 0.8 vccq i oh = -0.5 ma 0.8 vccq 0.8 vccq 0.8 vccq v ol output low voltage i ol = 2.0 ma vv vv i ol = 0.2 ma 0.2 i ol = 0.5 ma 0.2 vccq 0.2 vccq 0.2 vccq i active operating current v cc = 3.3 v 25 ma 25 ma 25 ma 25 ma i standby standby current v cc = 3.0 v a a a a v cc = 3.3 v 100 120 120 120 i deep sleep deep power down current 10 a 10 a 10 a 10 a i par 1/4 1/4 array par current 65 a 75 a 75 a 75 a i par 1/2 1/2 array par current 80 a 90 a 90 a 90 a
august 30, 2004 psram_type01_12_a1 psram type 1 103 advance information dc characteristics (64mb psram page mode) timing test conditions page mode performance grade -70 density 64mb psram symbol parameter conditions min max units v cc power supply 2.7 3.3 v v ih input high level 0.8 vccq v cc + 0.2 v v il input low level -0.2 0.2 vccq v i il input leakage current vin = 0 to v cc 1a i lo output leakage current oe = v ih or chip disabled 1a v oh output high voltage i oh = -1.0 ma v i oh = -0.2 ma i oh = -0.5 ma 0.8 vccq v ol output low voltage i ol = 2.0 ma v i ol = 0.2 ma i ol = 0.5 ma 0.2 vccq i active operating current v cc = 3.3 v 25 ma i standby standby current v cc = 3.0 v a v cc = 3.3 v 120 i deep sleep deep power down current 10 a i par 1/4 1/4 array par current 65 a i par 1/2 1/2 array par current 80 a item input pulse level 0.1 v cc to 0.9 v cc input rise and fall time 5ns input and output timing reference levels 0.5 v cc operating temperature -25c to +85c
104 psram type 1 psram_type01_12_a1 august 30, 2004 advance information output load circuit power up sequence after applying power, maintain a stable power supply for a minimum of 200 s after ce# > v ih . figure 21. output load circuit v cc 30 pf i/o 14.5k 14.5k output load
august 30, 2004 psram_type01_12_a1 psram type 1 105 advance information ac characteristics (4mb psram page mode) asynchronous performance grade -70 density 4mb psram 3 volt symbol parameter min max units read trc read cycle time 70 ns taa address access time 70 ns tco chip select to output 70 ns toe output enable to valid output 20 ns tba ub#, lb# access time 70 ns tlz chip select to low-z output 10 ns tblz ub#, lb# enable to low-z output 10 ns tolz output enable to low-z output 5ns thz chip enable to high-z output 020ns tbhz ub#, lb# disable to high-z output 020ns tohz output disable to high-z output 020ns toh output hold from address change 10 ns
106 psram type 1 psram_type01_12_a1 august 30, 2004 advance information write twc write cycle time 70 ns tcw chipselect to end of write 70 ns tas address set up time 0ns taw address valid to end of write 70 ns tbw ub#, lb# valid to end of write 70 ns twp write pulse width 55 ns twr write recovery time 0ns twhz write to output high-z 20 ns tdw data to write time overlap 25 ns tdh data hold from write time 0ns tow end write to output low-z 5 tow write high pulse width 7.5 ns other tpc page read cycle x tpa page address access time x twpc page write cycle x tcp chip select high pulse width x asynchronous performance grade -70 density 4mb psram 3 volt symbol parameter min max units
august 30, 2004 psram_type01_12_a1 psram type 1 107 advance information ac characteristics (8mb psram asynchronous) asynchronous version b c performance grade -55 -70 -70 density 8mb psram 8mb psram 8mb psram 3 volt symbol parameter min max units min max units min max units read trc read cycle time 55 ns 70 ns 70 ns taa address access time 55 ns 70 ns 70 ns tco chip select to output 55 ns 70 ns 70 ns toe output enable to valid output 30 ns 35 ns 20 ns tba ub#, lb# access time 55 ns 70 ns 70 ns tlz chip select to low-z output 5 ns 5 ns 10 ns tblz ub#, lb# enable to low-z output 5 ns 5 ns 10 ns tolz output enable to low-z output 5ns5ns5ns thz chip enable to high-z output 020ns025ns020ns tbhz ub#, lb# disable to high-z output 020ns025ns020ns tohz output disable to high-z output 020ns025ns020ns toh output hold from address change 10 ns 10 ns 10 ns
108 psram type 1 psram_type01_12_a1 august 30, 2004 advance information write twc write cycle time 55 ns 70 ns 70 ns tcw chip select to end of write 45 ns 55 ns 70 ns tas address set up time 0ns0ns0ns taw address valid to end of write 45 ns 55 ns 70 ns tbw ub#, lb# valid to end of write 45 ns 55 ns 70 ns twpwrite pulse width45ns55ns55ns twr write recovery time 0ns0ns0ns twhz write to output high-z 25 ns 25 20 ns tdw data to write time overlap 40 ns 40 ns 25 ns tdh data hold from write time 0ns0ns0ns tow end write to output low-z 555 tow write high pulse width xxnsxxnsxxns other tpc page read cycle x x x tpa page address access time xxx twpc page write cycle x x x tcp chip select high pulse width xxx asynchronous version b c performance grade -55 -70 -70 density 8mb psram 8mb psram 8mb psram 3 volt symbol parameter min max units min max units min max units
august 30, 2004 psram_type01_12_a1 psram type 1 109 advance information ac characteristics (16mb psram asynchronous) asynchronous performance grade -55 -70 density 16mb psram 16mb psram 3 volt symbol parameter min max units min max units read trc read cycle time 55 ns 70 ns taa address access time 55 ns 70 ns tco chip select to output 55 ns 70 ns toe output enable to valid output 30 ns 35 ns tba ub#, lb# access time 55 ns 70 ns tlz chip select to low-z output 5ns5ns tblz ub#, lb# enable to low-z output 5ns5ns tolz output enable to low-z output 5ns5ns thz chip enable to high-z output 025ns 025ns tbhz ub#, lb# disable to high-z output 025ns 025ns tohz output disable to high-z output 025ns 025ns toh output hold from address change 10 ns 10 ns
110 psram type 1 psram_type01_12_a1 august 30, 2004 advance information write twc write cycle time 55 ns 70 ns tcw chipselect to end of write 50 ns 55 ns tas address set up time 0ns0ns taw address valid to end of write 50 ns 55 ns tbw ub#, lb# valid to end of write 50 ns 55 ns twp write pulse width 50 ns 55 ns twr write recovery time 0ns0ns twhz write to output high-z 25 ns 25 ns tdw data to write time overlap 25 ns 25 ns tdh data hold from write time 0ns0ns tow end write to output low-z 55 tow write high pulse width xxnsxxns other tpc page read cycle x x tpa page address access time xx twpc page write cycle x x tcp chip select high pulse width xx asynchronous performance grade -55 -70 density 16mb psram 16mb psram 3 volt symbol parameter min max units min max units
august 30, 2004 psram_type01_12_a1 psram type 1 111 advance information ac characteristics (16mb psram page mode) page mode performance grade -60 -65 -70 density 16mb psram 16mb psram 16mb psram 3 volt symbol parameter min max units min max units min max units read trc read cycle time 60 20k ns 65 20k ns 70 20k ns taa address access time 60 ns 65 ns 70 ns tco chip select to output 60 ns 65 ns 70 ns toe output enable to valid output 25 ns 25 ns 25 ns tba ub#, lb# access time 60 ns 65 ns 70 ns tlz chip select to low-z output 10 ns 10 ns 10 ns tblz ub#, lb# enable to low-z output 10 ns 10 ns 10 ns tolz output enable to low-z output 5ns5ns5ns thz chip enable to high-z output 05ns05ns05ns tbhz ub#, lb# disable to high-z output 05ns05ns05ns tohz output disable to high-z output 05ns05ns05ns toh output hold from address change 5ns5ns5ns
112 psram type 1 psram_type01_12_a1 august 30, 2004 advance information write twc write cycle time 60 20k ns 65 20k ns 70 20k ns tcw chipselect to end of write 50 ns 60 ns 60 ns tas address set up time 0ns0ns0ns taw address valid to end of write 50 ns 60 ns 60 ns tbw ub#, lb# valid to end of write 50 ns 60 ns 60 ns twpwrite pulse width50ns50ns50ns twr write recovery time 0ns0ns0ns twhz write to output high-z 5ns 5ns 5ns tdw data to write time overlap 20 ns 20 ns 20 ns tdh data hold from write time 0ns0ns0ns tow end write to output low-z 555 tow write high pulse width 7.5 ns 7.5 ns 7.5 ns other tpc page read cycle 25 20k ns 25 20k ns 25 20k ns tpa page address access time 25 ns 25 ns 25 ns twpc page write cycle 25 20k ns 25 20k ns 25 20k ns tcp chip select high pulse width 10 ns 10 ns 10 ns page mode performance grade -60 -65 -70 density 16mb psram 16mb psram 16mb psram 3 volt symbol parameter min max units min max units min max units
august 30, 2004 psram_type01_12_a1 psram type 1 113 advance information ac characteristics (32mb psram page mode) page mode version c e performance grade -65 -60 -65 -70 density 32mb psram 32mb psram 32mb psram 32mb psram 3 volt symbol parameter min max units min max units min max units min max units read trc read cycle time 65 20k ns 60 20k ns 65 20k ns 70 20k ns taa address access time 65 ns 60 ns 65 ns 70 ns tco chip select to output 65 ns 60 ns 65 ns 70 ns toe output enable to valid output 20 ns 25 ns 25 ns 25 ns tba ub#, lb# access time 65 ns 60 ns 65 ns 70 ns tlz chip select to low-z output 10 ns 10 ns 10 ns 10 ns tblz ub#, lb# enable to low-z output 10 ns 10 ns 10 ns 10 ns tolz output enable to low-z output 5 ns5 ns 5 ns5 ns thz chip enable to high-z output 020ns0 5ns 0 5ns0 5ns tbhz ub#, lb# disable to high-z output 020ns0 5ns 0 5ns0 5ns tohz output disable to high-z output 020ns0 5ns 0 5ns0 5ns toh output hold from address change 5 ns5 ns 5 ns5 ns
114 psram type 1 psram_type01_12_a1 august 30, 2004 advance information write twc write cycle time 65 20k ns 60 20k ns 65 20k ns 70 20k ns tcw chipselect to end of write 55 ns 50 ns 60 ns 60 ns tas address set up time 0 ns0 ns 0 ns0 ns taw address valid to end of write 55 ns 50 ns 60 ns 60 ns tbw ub#, lb# valid to end of write 55 ns 50 ns 60 ns 60 ns twp write pulse width 55 20k ns 50 ns 50 ns 50 ns twr write recovery time 0 ns0 ns 0 ns0 ns twhz write to output high-z 5 ns 5 ns 5 ns 5 ns tdw data to write time overlap 25 ns 20 ns 20 ns 20 ns tdh data hold from write time 0 ns0 ns 0 ns0 ns tow end write to output low-z 55 5 5 tow write high pulse width 7.5 ns 7.5 ns 7.5 ns 7.5 ns other tpc page read cycle 25 20k ns 25 20k ns 25 20k ns 25 20k ns tpa page address access time 25 ns 25 ns 25 ns 25 ns twpc page write cycle 25 20k ns 25 20k ns 25 20k ns 25 20k ns tcp chip select high pulse width 10 ns 10 ns 10 ns 10 ns page mode version c e performance grade -65 -60 -65 -70 density 32mb psram 32mb psram 32mb psram 32mb psram 3 volt symbol parameter min max units min max units min max units min max units
august 30, 2004 psram_type01_12_a1 psram type 1 115 advance information ac characteristics (64mb psram page mode) page mode performance grade -70 density 64mb psram 3 volt symbol parameter min max units read trc read cycle time 70 20k ns taa address access time 70 ns tco chip select to output 70 ns toe output enable to valid output 25 ns tba ub#, lb# access time 70 ns tlz chip select to low-z output 10 ns tblz ub#, lb# enable to low-z output 10 ns tolz output enable to low-z output 5ns thz chip enable to high-z output 05ns tbhz ub#, lb# disable to high-z output 05ns tohz output disable to high-z output 05ns toh output hold from address change 5ns
116 psram type 1 psram_type01_12_a1 august 30, 2004 advance information timing diagrams read cycle write twc write cycle time 70 20k ns tcw chipselect to end of write 60 ns tas address set up time 0ns taw address valid to end of write 60 ns tbw ub#, lb# valid to end of write 60 ns twp write pulse width 50 20k ns twr write recovery time 0ns twhz write to output high-z 5ns tdw data to write time overlap 20 ns tdh data hold from write time 0ns tow end write to output low-z 5 tow write high pulse width 7.5 ns other tpc page read cycle 20 20k ns tpa page address access time 20 ns twpc page write cycle 20 20k ns tcp chip select high pulse width 10 ns figure 22. timing of read cycle (ce# = oe# = v il , we# = zz# = v ih ) page mode performance grade -70 density 64mb psram 3 volt symbol parameter min max units a ddress data out t rc t aa t oh data valid previous data valid
august 30, 2004 psram_type01_12_a1 psram type 1 117 advance information figure 23. timing waveform of read cycle (we# = zz# = v ih ) address lb#, ub# oe# data valid t rc t aa t co t hz t ohz t bhz t olz t oe t lz high-z data out t lb, t ub t blz ce#
118 psram type 1 psram_type01_12_a1 august 30, 2004 advance information figure 24. timing waveform of page mode read cycle (we# = zz# = v ih ) page address (a4 - a20) lb#, ub# oe# t aa t co t hz t ohz t bhz t olz t oe high-z data out t lb, t ub t blz, ce# word address (a0 - a3) t pa t rc t pgmax t pc
august 30, 2004 psram_type01_12_a1 psram type 1 119 advance information write cycle figure 25. timing waveform of write cycle (we# control, zz# = v ih ) figure 26. timing waveform of write cycle (ce# control, zz# = v ih ) addr es s dat a in ce# data valid t wc t aw t cw t wr t whz t dh high-z we# da ta out high-z t ow t as t wp t dw t bw lb#, ub# ad dr es s we# data valid t wc t aw t cw t wr t dh lb#, ub# dat a in high-z t as t wp t dw t bw da ta o ut t whz ce#
120 psram type 1 psram_type01_12_a1 august 30, 2004 advance information power savings modes (for 16m page mode, 32m and 64m only) there are several power savings modes. ? partial array self refresh ? temperature compensated refresh (64m) ? deep sleep mode ? reduced memory size (32m, 16m) the operation of the power saving modes ins controlled by the settings of bits contained in the mode register. this definition of the mode register is shown in figure 28 and the various bits are used to enable and disable the various low power modes as well as enabling page mode operation. the mode register is set by using the timings defined in figure xxx. partial array self refresh (par) in this mode of operation, the internal refresh operation can be restricted to a 16mb, 32mb, or 48mb portion of the array. the array partition to be refreshed is determined by the respective bit settings in the mode register. the register set - tings for the pasr operation are defined in table xxx. in this pasr mode, when zz# is active low, only the portion of the array that is set in the register is re - figure 27. timing waveform of page mode write cycle (zz# = v ih ) page a ddr es s (a4 - a 20) lb#, ub# we# t wp t cw t dw high-z dat a out t lbw, t ubw ce# wor d a ddr es s (a0 - a3 ) t wc t pwc t dh t pdw t pdh t pdw t pdh t as t pgmax
august 30, 2004 psram_type01_12_a1 psram type 1 121 advance information freshed. the data in the remainder of the array will be lost. the pasr operation mode is only available during standby time (zz# low) and once zz# is returned high, the device resumes full array refresh. all future pasr cycles will use the contents of the mode register that has been previously set. to change the ad - dress space of the pasr mode, the mode register must be reset using the previously defined procedures. for pasr to be activated, the register bit, a4 must be set to a one (1) value, ?pasr enabled?. if this is the case, pasr will be acti - vated 10 s after zz# is brought low. if the a4 register bit is set equal to zero (0), pasr will not be activated. temperature compensated refresh (for 64mb) in this mode of operation, the internal refresh rate can be optimized for the op - eration temperature used and this can then lower standby current. the dram array in the psram must be refreshed internally on a regular basis. at higher temperatures, the dram cell must be refreshed more often than at lower tem - peratures. by setting the temperature of operation in the mode register, this refresh rate can be optimized to yield the lowest standby current at the given op - erating temperature. there are four different temperature settings that can be programmed in to the psram. these are defined in figure 28 . deep sleep mode in this mode of operation, the internal refresh is turned off and all data integrity of the array is lost. deep sleep is entered by bringing zz# low with the a4 reg - ister bit set to a zero (0), ?deep sleep enabled?. if this is the case, deep sleep will be entered 10 s after zz# is brought low. the device will remain in this mode as long as zz# remains low. if the a4 register bit is set equal to one (1), deep sleep will not be activated. reduced memory size (for 32m and 16m) in this mode of operation, the 32mb psram can be operated as a 8mb or 16mb device. the mode and array size are determined by the settings in the va register. the va register is set according to the following timings and the bit settings in the table ?address patterns for rms?. the rms mode is enabled at the time of zz transitioning high and the mode remains active until the register is updated. to return to the full 32mb address space, the va register must be reset using the previously defined procedures. while operating in the rms mode, the unselected portion of the array may not be used. other mode register settings (for 64m) the page mode operation can also be enabled and disabled using the mode reg - ister. register bit a7 controls the operation of page mode and setting this bit to a one (1), enables page mode. if the register bit a7 is set to a zero (0), page mode operation is disabled.
122 psram type 1 psram_type01_12_a1 august 30, 2004 advance information figure 28. mode register figure 29. mode register updatetimings (ub#, lb#, oe# are don?t care) deep sleep enable/disabl e 0 = deep sleep enabled 1 = deep sleep disabled (default) par section 1 1 1 = top 1/4 array 1 1 0 = top 1/2 array 1 0 1 = top 3/4 array 1 0 0 = no par 0 1 1 = bottom 1/4 array 0 1 0 = bottom 1/2 array 0 0 1 = bottom 3/4 array 0 0 0 = full array (default) reserved must set to all 0 a21 - a8 a7 a6 a5 a4 a3 a2 a1 a0 page mode 0 = page mode disabled (default) 1 = page mode enabled te m p compensated refresh 1 0 = 15 o c 0 1 = 45 o c 0 0 = 70 o c 1 1 = 85 o c (default) array mode for zz# 0 = par (default) 1 = rms 64 mb 32 mb / 16 mb address zz# t wc t as ce# we# t zzwe t aw t wp t wr t cdzz
august 30, 2004 psram_type01_12_a1 psram type 1 123 advance information mode register update and deep sleep timings notes: 1. minimum cycle time for writing register is equal to speed grade of product. figure 30. deep sleep mode - entry/exit timings (for 64m) figure 31. deep sleep mode - entry/exit timings (for 32m and 16m) item symbol min max unit note chip deselect to zz# low t cdzz 5 ns zz# low to we# low t zzwe 10 500 ns write register cycle time t wc 70/85 ns 1 chip enable to end of write t cw 70/85 ns 1 address valid to end of write t aw 70/85 ns 1 write recovery time t wr 0 ns address setup time t as 0 ns write pulse width t wr 40 ns deep sleep pulse width t zzmin 10 s deep sleep recovery t r 200 s zz# t zzmin t cdzz t r ce# a4 zz# t wc t bw t as ce# we# t zzwe t aw t wp t wr t r t zzmin lb#, ub#
124 psram type 1 psram_type01_12_a1 august 30, 2004 advance information address patterns for pasr (a4=1) (64m) deep icc characteristics (for 64mb) address patterns for par (a3= 0, a4=1) (32m) a2 a1 a0 active section address space size density 1 1 1 top quarter of die 300000h-3fffffh 1mb x 16 16mb 1 1 0 top half of die 200000h-3fffffh 2mb x 16 32mb 1 0 1 reserved 1 0 0 no pasr none 0 0 0 1 1 bottom quarter of die 000000h-0fffffh 1mb x 16 16mb 0 1 0 bottom half of die 000000h-1fffffh 2mb x 16 32mb 0 0 1 reserved 0 0 0 full array 000000h-3fffffh 4mb x 16 64mb item symbol te s t array partition ty p max unit pasr mode standby current i pasr v in = v cc or 0v, chip disabled, t a = 85c none 10 a 1/4 array 60 1/2 array 80 full array 120 item symbol max temperature ty p max unit temperature compensated refresh current i tcr 15c 50 a 45c 60 70c 80 85c 120 item symbol te s t ty p max unit deep sleep current i zz v in = v cc or 0v, chip in zz# mode, t a = 25c 10 a a2 a1 a0 active section address space size density 0 1 1 one-quarter of die 000000h - 07ffffh 512kb x 16 8mb 0 1 0 one-half of die 000000h - 0fffffh 1mb x 16 16mb x 0 0 full die 000000h - 1fffffh 2mb x 16 32mb 1 1 1 one-quarter of die 180000h - 1fffffh 512kb x 16 8mb 1 1 0 one-half of die 100000h - 1fffffh 1mb x 16 16mb
august 30, 2004 psram_type01_12_a1 psram type 1 125 advance information address patterns for rms (a3 = 1, a4 = 1) (32m) a2 a1 a0 active section address space size density 0 1 1 one-quarter of die 000000h - 07ffffh 512kb x 16 8mb 0 1 0 one-half of die 000000h - 0fffffh 1mb x 16 16mb 1 1 1 one-quarter of die 180000h - 1fffffh 512kb x 16 8mb 1 1 0 one-half of die 100000h - 1fffffh 1mb x 16 16mb
126 psram type 1 psram_type01_12_a1 august 30, 2004 advance information low power icc characteristics (32m) address patterns for par (a3= 0, a4=1) (16m) address patterns for rms (a3 = 1, a4 = 1) (16m) low power icc characteristics (16m) item symbol te s t array partition ty p max unit par mode standby current i par v in = v cc or 0v, chip disabled, t a = 85 o c 1/4 array 75 a 1/2 array 90 a rms mode standby current i rmssb v in = v cc or 0v, chip disabled, t a = 85 o c 8mb device 75 a 16mb device 90 a deep sleep current i zz v in = v cc or 0v, chip in zz mode, t a = 85 o c 10 a a2 a1 a0 active section address space size density 0 1 1 one-quarter of die 00000h - 0ffffh 256kb x 16 4mb 0 1 0 one-half of die 00000h - 7ffffh 512kb x 16 8mb x 0 0 full die 00000h - fffffh 1mb x 16 16mb 1 1 1 one-quarter of die c0000h - ffffh 256kb x 16 4mb 1 1 0 one-half of die 80000h - 1fffffh 512kb x 16 8mb a2 a1 a0 active section address space size density 0 1 1 one-quarter of die 00000h - 0ffffh 256kb x 16 4mb 0 1 0 one-half of die 00000h - 7ffffh 512kb x 16 8mb 1 1 1 one-quarter of die c0000h - fffffh 256kb x 16 4mb 1 1 0 one-half of die 80000h - fffffh 512kb x 16 8mb item symbol te s t array partition ty p max unit par mode standby current i par v in = v cc or 0v, chip disabled, t a = 85 o c 1/4 array 65 a 1/2 array 80 rms mode standby current i rmssb v in = v cc or 0v, chip disabled, t a = 85 o c 4mb device 65 a 8mb device 80 deep sleep current i zz v in = v cc or 0v, chip in zz# mode, t a = 85 o c 10 a
may 4, 2004 psram_type07_13_a0 psram type 7 127 advance information psram type 7 16mb (1m word x 16-bit) 32mb (2m word x 16-bit) 64mb (4m word x 16-bit) cmos 1m/2m/4m-word x 16 bit fast cycle random access memory with low power sram interface features ? asynchronous sram interface ? fast access time ? tce = taa = 60ns max (16m) ? tce = taa = 65ns max (32m/64m) ? 8 words page access capability ? tpaa = 20ns max (32m/64m) ? low voltage operating condition ? vdd = +2.7v to +3.1v ? wide operating temperature ? ta = -30c to +85c ? byte control by lb and ub ? low power consumption ? idda1 = 20ma max (16m) ? idda1 = 30ma max (32m) ? idda1 =tbdma max (64m) ? idds1 = 100a max (16m) ? idds1 = 80a max (32m) ? idds1 = tbda max (64m) ? various power down mode ? sleep, 4m-bit partial or 8m-bit partial (32m) ? sleep, 8m-bit partial or 16m-bit partial (64m pin description pin name description a 21 to a 0 address input : a 19 to a 0 for 16m, a 20 to a 0 for 32m, a 21 to a 0 for 64m ce1# chip enable (low active) ce2# chip enable (high active) we# write enable (low active) oe# output enable (low active) ub# upper byte control (low active) lb# lower byte control (low active) dq 16 - 9 upper byte data input/output dq 8 - 1 lower byte data input/output v dd power supply
128 psram type 7 psram_type07_13_a0 may 4, 2004 advance information functional description legend: l = v il , h = v ih , x can be either v il or v ih , high-z = high impedence. notes: 1. should not be kept this logic condition longer than 1ms. please contact local spansion representative for the relaxation of 1ms limitation. 2. power down mode can be entered from standby state and all dq pins are in high-z state. data retention depends on the selection of power down program, 16m has data retetion in all modes except power down. refer to power down for the detail. 3. can be either v il or v ih but must be valid before read or write. 4. oe# can be v il during write operation if the following conditions are satisfied: (1) write pulse is initiated by ce1# (refer to ce1# controlled write timing), or cycle time of the previous operation cycle is satisfied. (2) oe# stays v il during write cycle power down (for 32m, 64m only) power down the power down is low power idle state controlled by ce2. ce2 low drives the device in power down mode and maintains low power idle state as long as ce2 is kept low. ce2 high resumes the device from power down mode. these devices have three power down mode. these can be proammed by series of read/write operation. each mode has follwoing features. v ss ground mode ce2# ce1# we# oe# lb# ub# a 21-0 dq 8-1 dq 16-9 standby (deselect) h h x x x x x high-z high-z output disable (note 1) hl h h x x note 3 high-z high-z output disable (no read) hl h h valid high-z high-z read (upper byte) h l valid high-z output valid read (lower byte) l h valid output valid high-z read (word) l l valid output valid output valid no write lh (note 4) h h valid invalid invalid write (upper byte) h l valid invalid input valid write (lower byte) l h valid input valid invalid write (word) l l valid input valid input valid power down l x x x x x x high-z high-z 32m 64m mode retention data retention address mode retention data retention address sleep (default) no n/a sleep (default) no n/a 4m partial 4m bit 00000h to 3ffffh 8m partial 8m bit 00000h to 7ffffh 8m partial 8m bit 00000h to 7ffffh 16m partial 16m bit 00000h to fffffh pin name description
may 4, 2004 psram_type07_13_a0 psram type 7 129 advance information the default state is sleep and it is the lowest power consumption but all data will be lost once ce2 is brought to low for power down. it is not required to program to sleep mode after power-up. power down program sequence the program requires total 6 read/write operation with unique address. between each read/write operation requires that device be in standby mode. following table shows the detail sequence. the first cycle is to read from most significient address (msb). the second and third cycle are to write back the data (rda) read by first cycle. if the second or third cycle is written into the different address, the program is cancelled and the data written by the second or third cycle is valid as a normal write operation. the forth and fifth cycle is to write to msb. the data of forth and fifth cycle is don?t-care. if the forth or fifth cycle is written into different address, the program is also cancelled but write data may not be wrote as normal write operation. the last cycle is to read from specific address key for mode selection. once this program sequence is performed from a partial mode to the other partial mode, the written data stored in memory cell array may be lost. so, it should per - form this program prior to regular read/write operation if partial mode is used. address key the address key has following format. cycle # operation address data 1st read 3fffffh (msb) read data (rda) 2nd write 3fffffh rda 3rd write 3fffffh rda 4th write 3fffffh don?t care (x) 5th write 3fffffh x 6th read address key read data (rdb) mode address 32m 64m a21 a20 a19 a18 - a0 binary sleep (default) sleep (default) 1 1 1 1 3fffffh 4m partial n/a 1 1 0 1 37ffffh 8m partial 8m partial 1 0 1 1 2fffffh n/a 16m partial 1 0 0 1 27ffffh
130 psram type 7 psram_type07_13_a0 may 4, 2004 advance information absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. recommended operating condi tions (see warning below) notes: 1. maximum dc voltage on input and i/o pins are v dd +0.2v. during voltage transitions, inputs may positive overshoot to v dd +1.0v for periods of up to 5 ns. 2. minimum dc voltage on input or i/o pins are -0.3v. during voltage transitions, inputs may negative overshoot v ss to -1.0v for periods of up to 5ns. warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the de - vice?s electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative before - hand. package capacitance test conditions: t a = 25c, f = 1.0 mhz item symbol value unit voltage of v dd supply relative to v ss v dd -0.5 to +3.6 v voltage at any pin relative to v ss v in , v out -0.5 to +3.6 v short circuit output current i out 50 ma storage temperature t stg -55 to +125 c parameter symbol min max unit supply voltage v dd 2.7 3.1 v v ss 0 0 v high level input voltage (note 1) v ih v dd 0.8 v dd +0.2 v high level input voltage (note 1) v il -0.3 v dd 0.2 v ambient temperature t a -30 85 c symbol description te s t s e t u p ty p max unit c in1 address input capacitance v in = 0v ? 5 pf c in2 control input capacitance v in = 0v ? 5 pf c io data input/output capacitance v io = 0v ? 8 pf
may 4, 2004 psram_type07_13_a0 psram type 7 131 advance information dc characteristics (under recomm ended conditions unless otherwise noted) notes: 1. all voltages are referenced to v ss . 2. dc characteristics are measured after following power-up timing. 3. i out depends on the output load conditions. parameter symbol test conditions 16m 32m 64m unit min. max. min. max. min. max. input leakage current i li v in = v ss to v dd -1.0 +1.0 -1.0 +1.0 -1.0 +1.0 a output leakage current i lo v out = v ss to v dd , output disable -1.0 +1.0 -1.0 +1.0 -1.0 +1.0 a output high voltage level v oh v dd = v dd (min), i oh = ? 0.5ma 2.2 ? 2.4 ? 2.4 ? v output low voltage level v ol i ol = 1ma ? 0.4 ? 0.4 ? 0.4 v v dd power down current i ddps v dd = v dd(26) max., v in = v ih or v il , ce2 0.2v sleep 10 ? 10 ? tbd a i ddp4 4m partial n/a ? 40 n/a a i ddp8 8m partial n/a ? 50 ? tbd a i ddp16 16m partial n/a n/a ? tbd a v dd standby current i dds v dd = v dd(26) max., v in = v ih or v il ce 1 = ce2 = v ih ? 1 ? 1.5 ? tbd ma i dds1 v dd = v dd(26) max., v in 0.2v or v in v dd ? 0.2v, ce 1 = ce2 v dd ? 0.2v ? 100 ? 80 ? tbd a v dd active current i dda1 v dd = v dd(26) max., v in = v ih or v il , ce 1 = v il and ce2= v ih , i out =0ma t rc / t wc = minimum ? 20 ? 30 ? tbd ma i dda2 t rc / t wc = 1 s ? 3 ? 3 ? tbd ma v dd page read current i dda3 v dd = v dd(26) max., v in = v ih or v il , ce 1 = v il and ce2= v ih , i out =0ma, t prc = min. n/a ? 10 ? tbd ma
132 psram type 7 psram_type07_13_a0 may 4, 2004 advance information ac characteristics (under recomme nded operating conditions unless otherwise noted) read operation notes: 1. maximum value is applicable if ce#1 is kept at low without change of address input of a3 to a21. if needed by system operation, please contact local spansion representative for the relaxation of 1s limitation. 2. address should not be changed within minimum t rc . 3. the output load 50pf. 4. the output load 5pf. parameter symbol 16m 32m 64m unit notes min. max. min. max. read cycle time t rc 70 1000 65 1000 65 1000 ns 1, 2 ce1# access time t ce ? 60 ? 65 ? 65 ns 3 oe# access time t oe ? 40 ? 40 ? 40 ns 3 address access time t aa ? 60 ? 65 ? 65 ns 3, 5 lb# / ub# access time t ba ? 30 ? 30 ? 30 ns 3 page address access time t paa n/a ? 20 ? 20 ns 3,6 page read cycle time t prc n/a 20 1000 20 1000 ns 1, 6, 7 output data hold time t oh 5 ? 5 ? 5 ? ns 3 ce1# low to output low-z t clz 5 ? 5 ? 5 ? ns 4 oe# low to output low-z t olz 0 ? 0 ? 0 ? ns 4 lb# / ub# low to output low-z t blz 0 ? 0 ? 0 ? ns 4 ce1# high to output high-z t chz ? 20 ? 20 ? 20 ns 3 oe# high to output high-z t ohz ? 20 ? 15 ? 20 ns 3 lb# / ub# high to output high-z t bhz ? 20 ? 20 ? 20 ns 3 address setup time to ce1# low t asc -5 ? ?5 ? ?5 ? ns address setup time to oe# low t aso 10 ? 10 ? 10 ? ns address invalid time t ax ? 10 ? 10 ? 10 ns 5, 8 address hold time from ce1# high t chah -6 ? ?6 ? ?6 ? ns 9 address hold time from oe# high t ohah -6 ? ?6 ? ?6 ? ns we# high to oe# low time for read t whol 10 1000 12 ? 12 ? ns 10 ce1# high pulse width t cp 10 ? 12 ? 12 ? ns
may 4, 2004 psram_type07_13_a0 psram type 7 133 advance information 5. applicable to a3 to a21 (32m and 64m) when ce1# is kept at low. 6. applicable only to a0, a1 and a2 (32m and 64m) wh en ce1# is kept at low for the page address access. 7. in case page read cycle is continued with keeping ce1# stays low, ce1# must be brought to high within 4s. in other words, page read cycle must be closed within 4s. 8. applicable when at least two of address inputs among applicable are switched from previous state. 9. t rc (min) and t prc (min) must be satisfied. 10. if actual value of t whol is shorter than specified minimum values, the actual t aa of following read may become longer by the amount of subtracting actual value from specified minimum value.
134 psram type 7 psram_type07_13_a0 may 4, 2004 advance information ac characteristics write operation notes: 1. maximum value is applicable if ce1# is kept at low without any address change. if the relaxation is needed by system operation, please contact local spansion representative for the relaxation of 1s limitation. 2. minimum value must be equal or greater than the sum of write pulse (t cw , t wp or t bw ) and write recovery time (t wr ). 3. write pulse is defined from high to low transition of ce1#, we#, or lb#/ub#, whichever occurs last. 4. applicable for byte mask only. byte mask setup time is defined to the high to low transition of ce1# or we# whichever occurs last. 5. applicable for byte mask only. byte mask hold time is defined from the low to high transition of ce1# or we# whichever occurs first. 6. write recovery is defined from low to high transiti on of ce1#, we#, or lb#/ub#, whichever occurs first. 7. t wph minimum is absolute minimum value for device to detect high level. and it is defined at minimum v ih level. 8. if oe# is low after minimum t ohcl , read cycle is initiated. in other words, oe# must be brought to high within 5ns after ce1# is brought to low. once read cycle is initiated, new write pulse should be input after minimum t rc is met. 9. if oe# is low after new address input, read cycle is initiated. in other word, oe# must be brought to high at the same time or before new address valid. once read cycle is initiated, new write pulse should be input after minimum t rc is met and data bus is in high-z. parameter symbol 16m 32m 64m unit notes min. max. min. max. min. max. write cycle time t wc 70 1000 65 1000 65 1000 ns 1,2 address setup time t as 0 ? 0 ? 0 ? ns 3 ce1# write pulse width t cw 45 ? 40 ? 40 ? ns 3 we# write pulse width t wp 45 ? 40 ? 40 ? ns 3 lb#/ub# write pulse width t bw 45 ? 40 ? 40 ? ns 3 lb#/ub# byte mask setup time t bs -5 ? ?5 ? ?5 ? ns 4 lb#/ub# byte mask hold time t bh -5 ? ?5 ? ?5 ? ns 5 write recovery time t wr 0 ? 0 ? 0 ? ns 6 ce1# high pulse width t cp 10 ? 12 ? 12 ? ns we# high pulse width t whp 7.5 1000 7.5 1000 7.5 1000 ns 7 lb#/ub# high pulse width t bhp 10 1000 12 1000 12 1000 ns data setup time t ds 15 ? 12 ? 12 ? ns data hold time t dh 0 ? 0 ? 0 ? ns oe# high to ce1# low setup time for write t ohcl -5 ? ?5 ? ?5 ? ns 8 oe# high to address setup time for write t oes 0 ? 0 ? 0 ? ns 9 lb# and ub# write pulse overlap t bwo 30 ? 30 ? 30 ? ns
may 4, 2004 psram_type07_13_a0 psram type 7 135 advance information ac characteristics power down parameters notes: 1. applicable also to power-up. 2. applicable when 4m and 8m partial mode is programmed. other timing parameters notes: 1. some data might be written into any address location if t chwx (min) is not satisfied. 2. the input transition time (t t ) at ac testing is 5ns as shown in below. if actual tt is longer than 5ns, it may violate ac specification of some timing parameters. parameter symbol 16m 32m 64m unit note min. max. min. max. min. max. ce2 low setup time for power down entry t csp 10 ? 10 ? 10 ? ns ce2 low hold time after power down entry t c2lp 80 ? 65 ? 65 ? ns ce1# high hold time following ce2 high after power down exit [sleep mode only] t chh 300 ? 300 ? 300 ? s 1 ce1# high hold time following ce2 high after power down exit [not in sleep mode] t chhp n/a 1 ? 1 ? s 2 ce1# high setup time following ce2 high after power down exit t chs 0 ? 0 ? 0 ? ns 1 parameter symbol 16m 32m 64m unit note min. max. min. max. min. max. ce 1# hi gh to oe # i nval i d ti me for standby entry t chox 10 ? 10 ? 10 ? ns ce1# high to we# invalid time for standby entry t chwx 10 ? 10 ? 10 ? ns 1 ce2 low hold time after power-up t c2lh n/a 50 ? 50 ? s ce1# high hold time following ce2 high after power-up t chh 300 ? 300 ? 300 ? s input transition time t t 1 25 1 25 1 25 ns 2
136 psram type 7 psram_type07_13_a0 may 4, 2004 advance information ac characteristics ac test conditions ac measurement output load circuit symbol description te s t s e t u p value unit note v ih input high level v dd * 0.8 v v il input low level v dd * 0.2 v v ref input timing measurement level v dd * 0.5 v t t input transition time between v il and v ih 5 ns figure 32. ac output load circuit device under test v dd v ss out 0.1 f 50pf
may 4, 2004 psram_type07_13_a0 psram type 7 137 advance information timing diagrams read timings note: this timing diagram assumes ce2=h and we#=h. note: this timing digaram assumes ce2=h and we#=h. figure 33. read timing #1 (baisc timing) figure 34. read timing #2 (oe# address access t ce valid data output address ce1# dq (output) oe# t chz t rc t olz t chah t cp address valid t asc t asc t ohz t oh t bhz lb#/ ub# t oe t ba t blz t clz t aa valid data output address ce 1# dq (output) t ohz t oe t rc t olz address valid valid data output address valid t rc t oh t oh oe# t ax low t aa t ohah t aso lb#/ub#
138 psram type 7 psram_type07_13_a0 may 4, 2004 advance information note: this timing diagram assumes ce2=h and we#=h. note: this timing diagram assumes ce2=h and we#=h. figure 35. read timing #3 (lb#/ub# byte access) figure 36. read timing #4 (page address access after ce1# control access for 32m and 64m only) t aa valid data output address dq1-8 (output) ub# t bhz t ba t rc t blz address valid valid data output t bhz t oh lb# t ax low t ba t ax dq9-16 (output) t blz t ba t blz t oh t bhz t oh valid data output ce1#, oe# valid data output (normal access) a ddress (a2-a0) ce1# dq (output) oe# t chz t ce t rc t clz address valid valid data output (page access) address valid t prc t oh t oh t chah t paa a ddress (a21-a3) address valid t paa t oh t prc t paa t prc t oh address valid address valid t rc t asc lb#/ub#
may 4, 2004 psram_type07_13_a0 psram type 7 139 advance information notes: 1. this timing diagram assumes ce2=h and we#=h. 2. either or both lb# and ub# must be low when both ce1# and oe# are low. write timings note: this timing diagram assumes ce2=h. figure 37. read timing #5 (random and page address access for 32m and 64m only) figure 38. write timing #1 (basic timing) valid data output (normal access) a ddress (a2-a0) ce 1# dq (output) oe# t oe t rc t olz t blz t aa valid data output (page access) address valid t prc t oh t oh t rc t paa a ddress (a21-a3) address valid t aa t oh address valid t rc t paa t prc t oh address valid address valid t rc t ax t ax t ba address valid low t aso lb#/ub# t as valid data input a ddress ce1# dq (input) we# t dh t ds t wc t wr t wp t cw lb#, ub# t as t bw address valid t as t as t wr oe# t ohcl t as t as t wr t cp t whp t bhp
140 psram type 7 psram_type07_13_a0 may 4, 2004 advance information note: this timing diagram assumes ce2=h. note: this timing diagram assumes ce2=h and oe#=h. figure 39. write timing #2 (we# control) figure 40. write timing #3-1 (we#/lb#/ub# byte write control) t as a ddress we# ce1# t wc t wr t wp lb#, ub# address valid t as t wr t wp valid data input dq (input) t dh t ds oe# t oes t ohz t wc valid data input t dh t ds low address valid t ohah t whp t as a ddress we# ce1# t wc t wr t wp lb# address valid t as t wr t wp valid data input dq1-8 (input) t dh t ds ub# t wc t dh t ds low address valid dq9-16 (input) t bs t bh t bs t bh t whp
may 4, 2004 psram_type07_13_a0 psram type 7 141 advance information note: this timing diagram assumes ce2=h and oe#=h. note: this timing diagram assumes ce2=h and oe#=h. figure 41. write timing #3-2 (we#/lb#/ub# byte write control) figure 42. write timing #3-3 (we#/lb#/ub# byte write control) t as a ddress we# ce1# t wc t wr t bw lb# address valid t as t wr t bw valid data input dq1-8 (input) t dh t ds ub# t wc valid data input t dh t ds low address valid dq9-16 (input) t bs t bh t bs t bh t whp t as a ddress we# ce1# t wc t wr t bw lb# address valid t as t wr t bw valid data input dq1-8 (input) t dh t ds ub# t wc valid data input t dh t ds low address valid dq9-16 (input) t bs t bh t bs t bh t whp
142 psram type 7 psram_type07_13_a0 may 4, 2004 advance information note: this timing diagram assumes ce2=h and oe#=h. read/write timings notes: 1. this timing diagram assumes ce2=h. 2. write address is valid from either ce1# or we# of last falling edge. figure 43. write timing #3-4 (we#/lb#/ub# byte write control) figure 44. read/write timing #1-1 (ce1# control) t as a ddress we# ce1# t wc t wr t bw lb# address valid t as t wr t bw dq1-8 (input) t dh t ds ub# t wc t dh t ds low address valid dq9-16 (input) t dh t ds t as t wr t bw t as t wr t bw t dh t ds valid data input valid data input valid data input valid data input t bwo t bwo t bhp t bhp read data output a ddress ce1# dq we# t wc t cw oe# t ohcl ub#, lb# t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wr t chah t dh t clz t oh
may 4, 2004 psram_type07_13_a0 psram type 7 143 advance information notes: 1. this timing diagram assumes ce2=h. 2. oe# can be fixed low during write operation if it is ce1# controlled write at read-write-read sequence. notes: 1. this timing diagram assumes ce2=h. 2. ce1# can be tied to low for we# and oe# controlled operation. figure 45. read / write timing #1-2 (ce1#/we#/oe# control) figure 46. read / write timing #2 (oe#, we# control) read data output a ddress ce1# dq we# t wc t wp oe# t ohcl ub#, lb# t oe t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wr t chah t dh t olz t oh read data output read data output a ddress ce1# dq we# t wc t wp oe# ub#, lb# t oe write address t as t rc write data input t ds t ohz t oh t aa read address t wr t dh t olz t oh read data output t ohz low t aso t ohah t oes t ohah t whol
144 psram type 7 psram_type07_13_a0 may 4, 2004 advance information notes: 1. this timing diagram assumes ce2=h. 2. ce1# can be tied to low for we# and oe# controlled operation. note: the t c2lh specifies after v dd reaches specified minimum level. figure 47. read / write timing #3 (oe#, we#, lb#, ub# control) figure 48. power-up timing #1 read data output a ddress ce1# dq we# t wc t bw oe# ub#, lb# t ba write address t as t rc write data input t ds t bhz t oh t aa read address t dh t blz t oh read data output t bhz low t aso t ohah t ohah t oes t whol t wr t c2lh ce1# v dd v dd min 0v ce2 t chh t chs
may 4, 2004 psram_type07_13_a0 psram type 7 145 advance information note: the t chh specifies after v dd reaches specified minimum level and applicable to both ce1# and ce2. note: this power down mode can be also used as a reset timing if power-up timing above could not be satisfied and power-down program was not performed prior to this reset. note: both t chox and t chwx define the earliest entry timing for standby mode. if either of timing is not satisfied, it takes t rc (min) period for standby mode from ce1# low to high transition. figure 49. power-up timing #2 figure 50. power down entry and exit timing figure 51. standby entry timing after read or write ce1# v dd v dd min 0v ce2 t chh t csp ce1# power down entry ce2 t c2lp t chh (t chhp ) power down mode power down exit t chs dq high-z t chox ce1# oe# we# active (read) standby active (write) standby t chwx
146 psram type 7 psram_type07_13_a0 may 4, 2004 advance information notes: 1. the all address inputs must be high from cycle #1 to #5. 2. the address key must confirm the format specified in page 129. if not, the operation and data are not guaranteed. 3. after t cp following cycle #6, the power down program is completed and returned to the normal operation. figure 52. power down program timing (for 32m/64m only) address ce1# dq* 3 we# t rc oe# lb#, ub# rda msb* 1 msb* 1 msb* 1 msb* 1 msb* 1 key* 2 t wc t wc t wc t wc t rc t cp t cp t cp t cp t cp t cp * 3 cycle #1 cycle #2 cycle #3 cycle #4 cycle #5 cycle #6 rda rda x x rdb
december 7, 2004 s71gl512_256_128nb0_00_a1 147 advance information revision summary revision a (august 24, 2004) initial release. revision a1 (december 7, 2004) connection diagrams. added 64-ball pinout. ordering information updated the opn table. valid combinations tables updated all tables. colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and c ould lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerabl e ( i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages ari sing in connection with above-men- tioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, dam age or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain re strictions on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any oth er country, the prior au- thorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion product under development by spansion llc. spansion llc reserves the right to change or discontinue work on any product without notice. the information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion llc assumes no liability for any damage s of any kind arising out of the use of the information in this document. copyright ? 2004 spansion llc. all rights reserved. spansion, the spansion logo, mirrorbit, combinations thereof, and expressfl ash are trademarks of span- sion llc. other company and product names used in this publication are for identification purposes only and may be trademarks o f their respective compa- nies.

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